75f51fc787
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@41073 a95241bf-73f2-0310-859d-f6bbb57e9c96
445 lines
12 KiB
C
445 lines
12 KiB
C
/*
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* Copyright 2006-2009, Haiku, Inc. All Rights Reserved.
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* Distributed under the terms of the MIT License.
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*
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* Authors:
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* Axel Dörfler, axeld@pinc-software.de
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* Alexander von Gluck IV, kallisti5@unixzen.com
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*/
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#ifndef RADEON_HD_H
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#define RADEON_HD_H
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#include "lock.h"
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#include <Accelerant.h>
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#include <Drivers.h>
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#include <PCI.h>
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#define VENDOR_ID_ATI 0x1002
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#define RADEON_TYPE_FAMILY_MASK 0xf000
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#define RADEON_TYPE_GROUP_MASK 0xfff0
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#define RADEON_TYPE_MODEL_MASK 0xffff
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#define DEVICE_NAME "radeon_hd"
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#define RADEON_ACCELERANT_NAME "radeon_hd.accelerant"
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struct DeviceType {
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uint32 type;
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DeviceType(int t)
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{
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type = t;
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}
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DeviceType& operator=(int t)
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{
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type = t;
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return *this;
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}
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bool InFamily(uint32 family) const
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{
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return (type & RADEON_TYPE_FAMILY_MASK) == family;
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}
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bool InGroup(uint32 group) const
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{
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return (type & RADEON_TYPE_GROUP_MASK) == group;
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}
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bool IsModel(uint32 model) const
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{
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return (type & RADEON_TYPE_MODEL_MASK) == model;
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}
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};
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// info about PLL on graphics card
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struct pll_info {
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uint32 reference_frequency;
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uint32 max_frequency;
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uint32 min_frequency;
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uint32 divisor_register;
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};
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struct ring_buffer {
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struct lock lock;
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uint32 register_base;
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uint32 offset;
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uint32 size;
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uint32 position;
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uint32 space_left;
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uint8* base;
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};
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struct overlay_registers;
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struct radeon_shared_info {
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area_id mode_list_area; // area containing display mode list
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uint32 mode_count;
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display_mode current_mode;
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uint32 bytes_per_row;
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uint32 bits_per_pixel;
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uint32 dpms_mode;
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area_id registers_area; // area of memory mapped registers
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uint8* status_page;
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addr_t physical_status_page;
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uint8* graphics_memory;
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addr_t physical_graphics_memory;
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uint32 graphics_memory_size;
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addr_t frame_buffer;
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uint32 frame_buffer_offset;
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struct lock accelerant_lock;
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struct lock engine_lock;
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ring_buffer primary_ring_buffer;
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int32 overlay_channel_used;
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bool overlay_active;
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uint32 overlay_token;
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addr_t physical_overlay_registers;
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uint32 overlay_offset;
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bool hardware_cursor_enabled;
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sem_id vblank_sem;
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uint8* cursor_memory;
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addr_t physical_cursor_memory;
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uint32 cursor_buffer_offset;
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uint32 cursor_format;
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bool cursor_visible;
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uint16 cursor_hot_x;
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uint16 cursor_hot_y;
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DeviceType device_type;
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char device_identifier[32];
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struct pll_info pll_info;
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};
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//----------------- ioctl() interface ----------------
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// magic code for ioctls
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#define RADEON_PRIVATE_DATA_MAGIC 'rdhd'
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// list ioctls
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enum {
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RADEON_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
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RADEON_GET_DEVICE_NAME,
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RADEON_ALLOCATE_GRAPHICS_MEMORY,
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RADEON_FREE_GRAPHICS_MEMORY
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};
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// retrieve the area_id of the kernel/accelerant shared info
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struct radeon_get_private_data {
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uint32 magic; // magic number
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area_id shared_info_area;
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};
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// allocate graphics memory
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struct radeon_allocate_graphics_memory {
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uint32 magic;
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uint32 size;
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uint32 alignment;
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uint32 flags;
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uint32 buffer_base;
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};
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// free graphics memory
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struct radeon_free_graphics_memory {
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uint32 magic;
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uint32 buffer_base;
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};
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// ----------------------------------------------------------
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// Register definitions, taken from X driver
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// ATI r600 specific
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enum _r6xxRegs {
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/* MCLK */
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R6_MCLK_PWRMGT_CNTL = 0x620,
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/* I2C */
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R6_DC_I2C_CONTROL = 0x7D30, /* (RW) */
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R6_DC_I2C_ARBITRATION = 0x7D34, /* (RW) */
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R6_DC_I2C_INTERRUPT_CONTROL = 0x7D38, /* (RW) */
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R6_DC_I2C_SW_STATUS = 0x7d3c, /* (RW) */
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R6_DC_I2C_DDC1_SPEED = 0x7D4C, /* (RW) */
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R6_DC_I2C_DDC1_SETUP = 0x7D50, /* (RW) */
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R6_DC_I2C_DDC2_SPEED = 0x7D54, /* (RW) */
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R6_DC_I2C_DDC2_SETUP = 0x7D58, /* (RW) */
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R6_DC_I2C_DDC3_SPEED = 0x7D5C, /* (RW) */
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R6_DC_I2C_DDC3_SETUP = 0x7D60, /* (RW) */
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R6_DC_I2C_TRANSACTION0 = 0x7D64, /* (RW) */
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R6_DC_I2C_TRANSACTION1 = 0x7D68, /* (RW) */
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R6_DC_I2C_DATA = 0x7D74, /* (RW) */
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R6_DC_I2C_DDC4_SPEED = 0x7DB4, /* (RW) */
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R6_DC_I2C_DDC4_SETUP = 0x7DBC, /* (RW) */
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R6_DC_GPIO_DDC4_MASK = 0x7E00, /* (RW) */
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R6_DC_GPIO_DDC4_A = 0x7E04, /* (RW) */
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R6_DC_GPIO_DDC4_EN = 0x7E08, /* (RW) */
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R6_DC_GPIO_DDC1_MASK = 0x7E40, /* (RW) */
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R6_DC_GPIO_DDC1_A = 0x7E44, /* (RW) */
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R6_DC_GPIO_DDC1_EN = 0x7E48, /* (RW) */
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R6_DC_GPIO_DDC1_Y = 0x7E4C, /* (RW) */
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R6_DC_GPIO_DDC2_MASK = 0x7E50, /* (RW) */
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R6_DC_GPIO_DDC2_A = 0x7E54, /* (RW) */
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R6_DC_GPIO_DDC2_EN = 0x7E58, /* (RW) */
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R6_DC_GPIO_DDC2_Y = 0x7E5C, /* (RW) */
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R6_DC_GPIO_DDC3_MASK = 0x7E60, /* (RW) */
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R6_DC_GPIO_DDC3_A = 0x7E64, /* (RW) */
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R6_DC_GPIO_DDC3_EN = 0x7E68, /* (RW) */
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R6_DC_GPIO_DDC3_Y = 0x7E6C /* (RW) */
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};
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// cursor
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#define RADEON_CURSOR_CONTROL 0x70080
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#define RADEON_CURSOR_BASE 0x70084
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#define RADEON_CURSOR_POSITION 0x70088
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#define RADEON_CURSOR_PALETTE 0x70090 // (- 0x7009f)
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#define RADEON_CURSOR_SIZE 0x700a0
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#define CURSOR_ENABLED (1UL << 31)
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#define CURSOR_FORMAT_2_COLORS (0UL << 24)
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#define CURSOR_FORMAT_3_COLORS (1UL << 24)
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#define CURSOR_FORMAT_4_COLORS (2UL << 24)
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#define CURSOR_FORMAT_ARGB (4UL << 24)
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#define CURSOR_FORMAT_XRGB (5UL << 24)
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#define CURSOR_POSITION_NEGATIVE 0x8000
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#define CURSOR_POSITION_MASK 0x3fff
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// overlay flip
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#define COMMAND_OVERLAY_FLIP (0x11 << 23)
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#define COMMAND_OVERLAY_CONTINUE (0 << 21)
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#define COMMAND_OVERLAY_ON (1 << 21)
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#define COMMAND_OVERLAY_OFF (2 << 21)
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#define OVERLAY_UPDATE_COEFFICIENTS 0x1
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// 2D acceleration
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#define XY_COMMAND_SOURCE_BLIT 0x54c00006
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#define XY_COMMAND_COLOR_BLIT 0x54000004
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#define XY_COMMAND_SETUP_MONO_PATTERN 0x44400007
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#define XY_COMMAND_SCANLINE_BLIT 0x49400001
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#define COMMAND_COLOR_BLIT 0x50000003
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#define COMMAND_BLIT_RGBA 0x00300000
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#define COMMAND_MODE_SOLID_PATTERN 0x80
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#define COMMAND_MODE_CMAP8 0x00
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#define COMMAND_MODE_RGB15 0x02
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#define COMMAND_MODE_RGB16 0x01
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#define COMMAND_MODE_RGB32 0x03
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// display
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#define DISPLAY_CONTROL_ENABLED (1UL << 31)
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#define DISPLAY_CONTROL_GAMMA (1UL << 30)
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#define DISPLAY_CONTROL_COLOR_MASK (0x0fUL << 26)
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#define DISPLAY_CONTROL_CMAP8 (2UL << 26)
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#define DISPLAY_CONTROL_RGB15 (4UL << 26)
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#define DISPLAY_CONTROL_RGB16 (5UL << 26)
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#define DISPLAY_CONTROL_RGB32 (6UL << 26)
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// PCI bridge memory management
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// overlay
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#define RADEON_OVERLAY_UPDATE 0x30000
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#define RADEON_OVERLAY_TEST 0x30004
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#define RADEON_OVERLAY_STATUS 0x30008
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#define RADEON_OVERLAY_EXTENDED_STATUS 0x3000c
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#define RADEON_OVERLAY_GAMMA_5 0x30010
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#define RADEON_OVERLAY_GAMMA_4 0x30014
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#define RADEON_OVERLAY_GAMMA_3 0x30018
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#define RADEON_OVERLAY_GAMMA_2 0x3001c
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#define RADEON_OVERLAY_GAMMA_1 0x30020
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#define RADEON_OVERLAY_GAMMA_0 0x30024
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struct overlay_scale {
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uint32 _reserved0 : 3;
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uint32 horizontal_scale_fraction : 12;
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uint32 _reserved1 : 1;
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uint32 horizontal_downscale_factor : 3;
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uint32 _reserved2 : 1;
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uint32 vertical_scale_fraction : 12;
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};
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#define OVERLAY_FORMAT_RGB15 0x2
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#define OVERLAY_FORMAT_RGB16 0x3
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#define OVERLAY_FORMAT_RGB32 0x1
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#define OVERLAY_FORMAT_YCbCr422 0x8
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#define OVERLAY_FORMAT_YCbCr411 0x9
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#define OVERLAY_FORMAT_YCbCr420 0xc
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#define OVERLAY_MIRROR_NORMAL 0x0
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#define OVERLAY_MIRROR_HORIZONTAL 0x1
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#define OVERLAY_MIRROR_VERTICAL 0x2
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// The real overlay registers are written to using an update buffer
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struct overlay_registers {
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uint32 buffer_rgb0;
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uint32 buffer_rgb1;
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uint32 buffer_u0;
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uint32 buffer_v0;
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uint32 buffer_u1;
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uint32 buffer_v1;
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// (0x18) OSTRIDE - overlay stride
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uint16 stride_rgb;
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uint16 stride_uv;
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// (0x1c) YRGB_VPH - Y/RGB vertical phase
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uint16 vertical_phase0_rgb;
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uint16 vertical_phase1_rgb;
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// (0x20) UV_VPH - UV vertical phase
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uint16 vertical_phase0_uv;
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uint16 vertical_phase1_uv;
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// (0x24) HORZ_PH - horizontal phase
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uint16 horizontal_phase_rgb;
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uint16 horizontal_phase_uv;
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// (0x28) INIT_PHS - initial phase shift
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uint32 initial_vertical_phase0_shift_rgb0 : 4;
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uint32 initial_vertical_phase1_shift_rgb0 : 4;
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uint32 initial_horizontal_phase_shift_rgb0 : 4;
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uint32 initial_vertical_phase0_shift_uv : 4;
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uint32 initial_vertical_phase1_shift_uv : 4;
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uint32 initial_horizontal_phase_shift_uv : 4;
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uint32 _reserved0 : 8;
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// (0x2c) DWINPOS - destination window position
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uint16 window_left;
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uint16 window_top;
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// (0x30) DWINSZ - destination window size
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uint16 window_width;
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uint16 window_height;
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// (0x34) SWIDTH - source width
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uint16 source_width_rgb;
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uint16 source_width_uv;
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// (0x38) SWITDHSW - source width in 8 byte steps
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uint16 source_bytes_per_row_rgb;
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uint16 source_bytes_per_row_uv;
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uint16 source_height_rgb;
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uint16 source_height_uv;
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overlay_scale scale_rgb;
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overlay_scale scale_uv;
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// (0x48) OCLRC0 - overlay color correction 0
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uint32 brightness_correction : 8; // signed, -128 to 127
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uint32 _reserved1 : 10;
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uint32 contrast_correction : 9; // fixed point: 3.6 bits
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uint32 _reserved2 : 5;
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// (0x4c) OCLRC1 - overlay color correction 1
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uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits
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uint32 _reserved3 : 6;
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uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits
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uint32 _reserved4 : 5;
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// (0x50) DCLRKV - destination color key value
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uint32 color_key_blue : 8;
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uint32 color_key_green : 8;
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uint32 color_key_red : 8;
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uint32 _reserved5 : 8;
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// (0x54) DCLRKM - destination color key mask
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uint32 color_key_mask_blue : 8;
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uint32 color_key_mask_green : 8;
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uint32 color_key_mask_red : 8;
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uint32 _reserved6 : 7;
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uint32 color_key_enabled : 1;
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// (0x58) SCHRKVH - source chroma key high value
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uint32 source_chroma_key_high_red : 8;
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uint32 source_chroma_key_high_blue : 8;
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uint32 source_chroma_key_high_green : 8;
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uint32 _reserved7 : 8;
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// (0x5c) SCHRKVL - source chroma key low value
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uint32 source_chroma_key_low_red : 8;
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uint32 source_chroma_key_low_blue : 8;
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uint32 source_chroma_key_low_green : 8;
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uint32 _reserved8 : 8;
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// (0x60) SCHRKEN - source chroma key enable
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uint32 _reserved9 : 24;
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uint32 source_chroma_key_red_enabled : 1;
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uint32 source_chroma_key_blue_enabled : 1;
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uint32 source_chroma_key_green_enabled : 1;
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uint32 _reserved10 : 5;
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// (0x64) OCONFIG - overlay configuration
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uint32 _reserved11 : 3;
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uint32 color_control_output_mode : 1;
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uint32 yuv_to_rgb_bypass : 1;
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uint32 _reserved12 : 11;
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uint32 gamma2_enabled : 1;
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uint32 _reserved13 : 1;
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uint32 select_pipe : 1;
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uint32 slot_time : 8;
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uint32 _reserved14 : 5;
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// (0x68) OCOMD - overlay command
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uint32 overlay_enabled : 1;
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uint32 active_field : 1;
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uint32 active_buffer : 2;
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uint32 test_mode : 1;
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uint32 buffer_field_mode : 1;
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uint32 _reserved15 : 1;
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uint32 tv_flip_field_enabled : 1;
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uint32 _reserved16 : 1;
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uint32 tv_flip_field_parity : 1;
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uint32 source_format : 4;
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uint32 ycbcr422_order : 2;
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uint32 _reserved18 : 1;
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uint32 mirroring_mode : 2;
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uint32 _reserved19 : 13;
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uint32 _reserved20;
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uint32 start_0y;
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uint32 start_1y;
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uint32 start_0u;
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uint32 start_0v;
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uint32 start_1u;
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uint32 start_1v;
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uint32 _reserved21[6];
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#if 0
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// (0x70) AWINPOS - alpha blend window position
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uint32 awinpos;
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// (0x74) AWINSZ - alpha blend window size
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uint32 awinsz;
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uint32 _reserved21[10];
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#endif
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// (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough,
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// the next two registers switch the usual Y/RGB vs. UV order)
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uint16 horizontal_scale_uv;
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uint16 horizontal_scale_rgb;
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// (0xa4) UVSCALEV - vertical downscale
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uint16 vertical_scale_uv;
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uint16 vertical_scale_rgb;
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uint32 _reserved22[86];
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// (0x200) polyphase filter coefficients
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uint16 vertical_coefficients_rgb[128];
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uint16 horizontal_coefficients_rgb[128];
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uint32 _reserved23[64];
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// (0x500)
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uint16 vertical_coefficients_uv[128];
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uint16 horizontal_coefficients_uv[128];
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};
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struct hardware_status {
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uint32 interrupt_status_register;
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uint32 _reserved0[3];
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void* primary_ring_head_storage;
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uint32 _reserved1[3];
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void* secondary_ring_0_head_storage;
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void* secondary_ring_1_head_storage;
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uint32 _reserved2[2];
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void* binning_head_storage;
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uint32 _reserved3[3];
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uint32 store[1008];
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};
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#endif /* RADEON_HD_H */
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