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Author	SHA1	Message	Date
Jérôme Duval	46f7a54d8c	MSI: Use the effective APIC id of the boot CPU for the address destination. * This should only affect systems where the CPU ids aren't sequential (mostly non Intel). * Fixes #9807.	2013-07-29 17:36:03 +02:00
Michael Lotz	33fbe25496	* Add code to allocate and free interrupt vectors for message signaled interrupts (MSI). * Add the remaining IDT entries and redirection functions in the interrupt code. * Make the PIC end_of_interrupt() return a result to indicate whether the vector was handled by this PIC. If it isn't we now issue a apic_end_of_interrupt() in the assumption of apic local interrupt, MSI or IPI. This also removes the need for the gUsingIOAPIC global and doing manual apic_end_of_interrupt() calls in the SMP and timer code. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@36221 a95241bf-73f2-0310-859d-f6bbb57e9c96	2010-04-13 14:46:09 +00:00

Author

SHA1

Message

Date

Jérôme Duval

46f7a54d8c

MSI: Use the effective APIC id of the boot CPU for the address destination.

* This should only affect systems where the CPU ids aren't sequential (mostly
non Intel).
* Fixes #9807.

2013-07-29 17:36:03 +02:00

Michael Lotz

33fbe25496

* Add code to allocate and free interrupt vectors for message signaled

interrupts (MSI).
* Add the remaining IDT entries and redirection functions in the interrupt code.
* Make the PIC end_of_interrupt() return a result to indicate whether the vector
  was handled by this PIC. If it isn't we now issue a apic_end_of_interrupt()
  in the assumption of apic local interrupt, MSI or IPI. This also removes
  the need for the gUsingIOAPIC global and doing manual apic_end_of_interrupt()
  calls in the SMP and timer code.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@36221 a95241bf-73f2-0310-859d-f6bbb57e9c96

2010-04-13 14:46:09 +00:00

2 Commits