This detects everything up to ARMv6 right now. Need to check more
recent ARM ARMs for ARMv7 detection.
The detected details get passed on to the kernel, which can use
the pre-detected info for selecting right pagetable format and such.
Copyright removal of Axel done after agreement with Axel @ BeGeistert
that for files that were copy/pasted from x86 arch and then fully
replaced the implementation, removal of original copyright holder is
allowed, since their actual code is gone ;)
This is to make sure all ARM platforms will benefit from planned work on this
MMU/CPU code. The less code duplicated, the better.
Compile-tested for all supported ARM platforms
This also implements the fault handler correctly now, and cleans up the
exception handling. Seems a lot more stable now, no unexpected panics or
faults happening anymore.
* The only implementation that would accept more than 2 TB was the one in
scsi_disk. But even that one was limited to 63 TB.
* Now there is a new utility function devfs_compute_geometry_size() which
does it correctly for sizes up to 2^64 which should be good enough for
quite some time :-)
* This fixes bug #8992.
The lowest 4 bits of the MSR serves as a hint to the hardware to
favor performance or energy saving. 0 means a hint preference for
highest performance while 15 corresponds to the maximum energy
savings. A value of 7 translates into a hint to balance performance
with energy savings.
The default reset value of the MSR is 0. If BIOS doesn't intialize
the MSR, the hardware will run in performance state. This patch
initialize the MSR with value of 7 for balance between performance
and energy savings
Signed-off-by: Fredrik Holmqvist <fredrik.holmqvist@gmail.com>
* gPeripheralBase keeps track of the device
peripherals before and after mmu_init
* Add ability to disable mmu for troubleshooting
* Remove static FB_BASE, we actually don't know
where the FB is yet. (depends on firmware used)
* BCM2708 defines no longer assume 0x20 address
We will be throwing away the blob memory mapping
and using our own.
* Use existing blob mapping to turn GPIO led on pre mmu_init
* Remap MMU hardware addresses from 0x7E. We could map each device,
however the kernel will throw away the mappings again anyway. For
now we just map the whole range and use offsets.
* Serial uart no longer works, however at least
we know why now :). Serial driver now needs to
use mapped address.
* Use U-Boot mmu code as base
* This will be factored out someday into common arch mmu
code when we can read Flattened Device Trees
* Move mmu_init after serial_init.
Temporary change as we will want serial_init to use
memory mapped addresses... for debugging.
* introduce a DebugUART baseclass,
* rework 8250 and PL011 implementations from kallisti5 to inherit DebutUART,
* each arch should override the IO methods to access registers.
* on ARM registers are 32bit-aligned.
* U-Boot still works for the verdex target.
* rPi still compiles, needs testing.
* Still some more consolidation needed to allow runtime choice of the UART type (as read from FDT blobs for ex.).
* serial.cpp should probably mostly be made generic as well.
* didn't touch x86 or ppc yet.
* Enable/Disable makes more sense and matches
platform loader serial functions.
* Rework PL011 code after finding a PDF covering
the details of it.
* Rename UART global defines in loader to be more
exact about location
* This makes things a little more flexible and
the interface to use the uarts cleaner.
* May want to make a generic Uart wrapper
class in uart.h / uart.cpp and call drivers
as needed from there.
* Avoid name collisions
* This uart stuff may work better as a class at
some point, however I didn't want to rock the
u-boot boat *too* much as I don't have the
hardware to test.
* Add nested function wrappers to allow usage of other
uart drivers depending on board. We may want to use this
on other platforms at some point (haha, maybe)
* Make Kernel ARM UART slightly more generic
through (BOARD_UART_CLOCK) configured per board
* Add initial Raspberry Pi serial code
* Still rough and non-working
AMD C1E is a BIOS controlled C3 state. Certain processors families
may cut off TSC and the lapic timer when it is in a deep C state,
including C1E state, thus the cpu can't be waken up and system will hang.
This patch firstly adds the support of idle selection during boot. Then
it implements amdc1e_noarat_idle() routine which checks the MSR which
contains the C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27) before
executing the halt instruction, then clear them once set.
However intel C1E doesn't has such problem. AMD C1E is a BIOS controlled
C3 state. The difference between C1E and C3 is that transition into C1E
is not initiated by the operating system. System will enter C1E state
automatically when both cores enters C1 state. As for intel C1E, it
means "reduce CPU voltage before entering corresponding Cx-state".
This patch may fix#8111, #3999, #7562, #7940 and #8060
Copied from the description of #3999:
>but for some reason I hit the power button instead of the reset one. And
>the boot continued!!
The reason is CPUs are waken up once power button is hit.
Signed-off-by: Fredrik Holmqvist <fredrik.holmqvist@gmail.com>
* Prepend x86_ to non-static x86 code
* Add x86_init_fpu function to kernel header
* Don't init fpu multiple times on smp systems
* Verified fpu is still started on smp and non-smp
* SSE code still generates general protection faults
on smp systems though
* Rename init_sse to init_fpu and handle FPU setup.
* Stop trying to set up FPU before VM init.
We tried to set up the FPU before VM init, then
set it up again after VM init with SSE extensions,
this caused SSE and MMX applications to crash.
* Be more logical in FPU setup by detecting CPU flag prior
to enabling FPU. (it's unlikely Haiku will run on
a processor without a fpu... but lets be consistant)
* SSE2 gcc code now runs (faster even) without GPF
* tqh confirms his previously crashing mmx code now works
* The non-SSE FPU enable after VM init needs tested!
This allows to use the debug features of the guarded heap also on
allocations made through the object cache API. This is obivously
horrible for performance and uses up huge amounts of memory, so the
initial and grow sizes are adjusted accordingly.
Note that this is a rather simple hack, using the object_cache pointer
to transport the allocation size. The alignment is neglected completely.
This adds a pair of functions vm_prepare_kernel_area_debug_protection()
and vm_set_kernel_area_debug_protection() to set a kernel area up for
page wise protection and to actually protect individual pages
respectively.
It was already possible to read and write protect full areas via area
protection flags and not mapping any actual pages. For areas that
actually have mapped pages this doesn't work however as no fault, at
which the permissions could be checked, is generated on access.
These new functions use the debug helpers of the translation map to mark
individual pages as non-present without unmapping them. This allows them
to be "protected", i.e. causing a fault on read and write access. As they
aren't actually unmapped they can later be marked present again.
Note that these are debug helpers and have quite a few restrictions as
described in the comment above the function and is only useful for some
very specific and constrained use cases.
They can be used to mark pages as present/non-present without actually
unmapping them. Marking pages as non-present causes every access to
fault. We can use that for debugging as it allows us to "read protect"
individual kernel pages.
* The vm86 code or the code running in virtual 8086 mode may clobber the
%fs register that we use for the CPU dependent thread local storage
(TLS). Previously the vm86 code would simply restore %fs on exit, but
this doesn't always work. If the thread got unscheduled while running
in virtual 8086 mode and was then rescheduled on a different CPU, the
vm86 exit code would restore the %fs register with the TLS value of
the old CPU, causing anything using TLS in userland to crash later on.
Instead we skip the %fs register restore on exit (as do the other
interrupt return functions) and explicitly update the potentially
clobbered %fs by calling x86_set_tls_context(). This will repopulate
the %fs register with the TLS value for the right CPU. Fixes#8068.
* Made the static set_tls_context() into x86_set_tls_context() and made
it available to others to faciliate the above.
* Sync the vm86 specific interrupt code with the changes from hrev23370,
using the iframe pop macro to properly return. Previously what was
pushed in int_bottom wasn't poped on return.
* Account for the time update macro resetting the in_kernel flag and
reset it to 1, as we aren't actually returning to userland. This
didn't cause any harm though as only the time tracking is using that
flag so far.
* Some minor cleanup.
* AVLTreeMap::_GetKey(): Change return type from const Key& to Key, so
the strategy can do that as well and doesn't have have a Key object in
the node.
* Fix the Auto strategy: It was using the undefined _GetKey() instead
of GetKey().
both:
* Add Previous()/Next().
* Add Insert() version that returns a Node* instead of an Iterator.
* Add Remove() version that takes a Node* instead of a key.
TwoKeyAVLTree:
* Add GetIterator() version that takes an additional Node*, i.e.
initializing an iterator to point to the node.
* Add Iterator::CurrentNode().
