* The team and thread kernel structures have been renamed to Team and Thread
respectively and moved into the new BKernel namespace.
* Several (kernel add-on) sources have been converted from C to C++ since
private kernel headers are included that are no longer C compatible.
Changes after merging:
* Fixed gcc 2 build (warnings mainly in the scary firewire bus manager).
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@40196 a95241bf-73f2-0310-859d-f6bbb57e9c96
at boot, per cpu, detect the cpu, pull down all the relevant cpuid bits and
save them into the per-cpu structure. Changed most of the code scattered here
and there that reads the cpuid to use a new api, x86_check_feature, which looks
at the saved bits.
Also changed the system_info stuff to read from these bits.
While i was at it, refreshed all the bits to be current.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@20072 a95241bf-73f2-0310-859d-f6bbb57e9c96
code. The stack pointer was not adjusted, hence we were
overwriting the previous register value. But it looks like I
missed to check in the arch_cpu.h with the iframe structure
including the floating point registers anyway.
* Backported the ELF PPC relocation code from the boot loader to
the kernel.
* Fixed the PPC version of arch_thread_switch_kstack_and_call().
Apparently the signature had changed, but the assembly
implementation was not adjusted accordingly.
* sc prints more registers now (LR, CR, CTR, XER,...).
* Fixed several occurences of not-working fault handlers.
Apparently the compiler realized, that the "error" label was
never jumped to (by the code it knew), and optimized the
respective code away. Now we use a trick to make it think the
error label might actually be jumped to. I wonder whether the
x86 version has the same problem when being compiled with GCC4.
* Adopted the x86 page fault handling interrupt code.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@15933 a95241bf-73f2-0310-859d-f6bbb57e9c96
* Cloned iframe stack management from x86.
* Reimplemented arch_thread_{get,set}_current_thread(). The
thread structure is stored in SPRG2. It is set to NULL in
arch_cpu_preboot_init(), now. A non-null current thread
causes all kinds of undesired behavior in early boot code.
* We establish the address space mappings we know from the
Open Firmware as areas. At least those in kernel address
space. The ones in userland address space are tougher.
Fortunately on my Mac mini there aren't any save the
boot_loader stack, which is not needed any longer anyway.
* Added stack trace support to the kernel debugger. Mostly
cloned and adjusted the x86 code. Some bits are still
missing, like stack traces for other threads.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@15890 a95241bf-73f2-0310-859d-f6bbb57e9c96
The time base conversion factor is the 32 bit value
2^32 * 1000000 / time base frequency,
so the system time can be computed by
system time = time base * conversion factor / 2^32.
The expression in system_time() looks more complicated now, but is
actually much faster (factor 2.5 on my Mac mini). I'm positively
surprised, how good the assembly looks, that GCC 4 generates. There's
not that much potential for optimization by hand-coding the function.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@15863 a95241bf-73f2-0310-859d-f6bbb57e9c96
device in the Open Firmware implementation of boot loader and
pass its path to the kernel, where it's opened and used for
getting/setting the real time. The expensive atomic_*64() on PPC
32-bit make things a bit more complicated. Moreover, missing
64 bit multiplication and division instructions won't really
allow system_time() to be anywhere near as fast as on x86. :-/
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@15837 a95241bf-73f2-0310-859d-f6bbb57e9c96
bus, and time base frequency) in the PPC boot loader, and propagate
them to the kernel via kernel_args.
* Now we use the correct time base frequency for timer calculations.
* Implemented PPC specific system info stuff. Added a few PPC CPU
types to <OS.h>.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@15817 a95241bf-73f2-0310-859d-f6bbb57e9c96
the fact that I couldn't find ptesync in an otherwise more complete
documentation I downloaded yesterday made me suspicious.
* arch_cpu_global_TLB_invalidate() uses tlbia now. The instruction is
optional, but so is tlbie (how I understood it is that both exist,
when the architecture implementation has a TLB). And the former loop
looked just scary.
* Implemented arch_cpu_user_TLB_invalidate(). It does just the same as
arch_cpu_global_TLB_invalidate().
* Some changes with respect to synchronization required on page table
and segment register updates.
* Some more minor renaming. Pulled a new function
remove_page_table_entry() out of unmap_tmap().
* In arch_vm_translation_map_init_post_area() we do now remap the page
table into the kernel address space, if it was without before. The
page table might actually be a good application for BAT, though.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@15773 a95241bf-73f2-0310-859d-f6bbb57e9c96
Added constructors to block_address_translation and segment_descriptor
that will clear its memory (could be done more efficiently though, it just
uses memset()).
Added definitions for the MSR (machine state register).
Added tlbsync() macro (direct assembler call).
git-svn-id: file:///srv/svn/repos/haiku/trunk/current@5092 a95241bf-73f2-0310-859d-f6bbb57e9c96
Added an alternative page_table_entry::SecondaryHash() signature.
git-svn-id: file:///srv/svn/repos/haiku/trunk/current@4988 a95241bf-73f2-0310-859d-f6bbb57e9c96
They are only used if the architecture doesn't support them directly.
git-svn-id: file:///srv/svn/repos/haiku/trunk/current@4360 a95241bf-73f2-0310-859d-f6bbb57e9c96
