6c678c57c7
* Cloned iframe stack management from x86.
* Reimplemented arch_thread_{get,set}_current_thread(). The
thread structure is stored in SPRG2. It is set to NULL in
arch_cpu_preboot_init(), now. A non-null current thread
causes all kinds of undesired behavior in early boot code.
* We establish the address space mappings we know from the
Open Firmware as areas. At least those in kernel address
space. The ones in userland address space are tougher.
Fortunately on my Mac mini there aren't any save the
boot_loader stack, which is not needed any longer anyway.
* Added stack trace support to the kernel debugger. Mostly
cloned and adjusted the x86 code. Some bits are still
missing, like stack traces for other threads.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@15890 a95241bf-73f2-0310-859d-f6bbb57e9c96
175 lines
4.2 KiB
C
175 lines
4.2 KiB
C
/*
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** Copyright 2003-2004, Axel Dörfler, axeld@pinc-software.de. All rights reserved.
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** Distributed under the terms of the Haiku License.
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*/
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#ifndef _KERNEL_ARCH_PPC_CPU_H
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#define _KERNEL_ARCH_PPC_CPU_H
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#include <arch/ppc/arch_thread_types.h>
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#include <kernel.h>
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#define PAGE_SIZE 4096
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struct iframe {
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uint32 vector;
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uint32 srr0;
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uint32 srr1;
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uint32 dar;
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uint32 dsisr;
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uint32 lr;
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uint32 cr;
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uint32 xer;
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uint32 ctr;
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uint32 r31;
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uint32 r30;
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uint32 r29;
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uint32 r28;
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uint32 r27;
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uint32 r26;
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uint32 r25;
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uint32 r24;
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uint32 r23;
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uint32 r22;
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uint32 r21;
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uint32 r20;
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uint32 r19;
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uint32 r18;
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uint32 r17;
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uint32 r16;
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uint32 r15;
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uint32 r14;
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uint32 r13;
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uint32 r12;
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uint32 r11;
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uint32 r10;
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uint32 r9;
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uint32 r8;
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uint32 r7;
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uint32 r6;
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uint32 r5;
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uint32 r4;
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uint32 r3;
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uint32 r2;
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uint32 r1;
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uint32 r0;
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};
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enum machine_state {
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MSR_EXCEPTIONS_ENABLED = 1L << 15, // EE
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MSR_PRIVILEGE_LEVEL = 1L << 14, // PR
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MSR_FP_AVAILABLE = 1L << 13, // FP
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MSR_MACHINE_CHECK_ENABLED = 1L << 12, // ME
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MSR_EXCEPTION_PREFIX = 1L << 6, // IP
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MSR_INST_ADDRESS_TRANSLATION = 1L << 5, // IR
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MSR_DATA_ADDRESS_TRANSLATION = 1L << 4, // DR
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};
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struct block_address_translation;
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern uint32 get_sdr1(void);
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extern void set_sdr1(uint32 value);
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extern uint32 get_sr(void *virtualAddress);
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extern void set_sr(void *virtualAddress, uint32 value);
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extern uint32 get_msr(void);
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extern uint32 set_msr(uint32 value);
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extern uint32 get_pvr(void);
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extern void set_ibat0(struct block_address_translation *bat);
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extern void set_ibat1(struct block_address_translation *bat);
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extern void set_ibat2(struct block_address_translation *bat);
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extern void set_ibat3(struct block_address_translation *bat);
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extern void set_dbat0(struct block_address_translation *bat);
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extern void set_dbat1(struct block_address_translation *bat);
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extern void set_dbat2(struct block_address_translation *bat);
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extern void set_dbat3(struct block_address_translation *bat);
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extern void get_ibat0(struct block_address_translation *bat);
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extern void get_ibat1(struct block_address_translation *bat);
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extern void get_ibat2(struct block_address_translation *bat);
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extern void get_ibat3(struct block_address_translation *bat);
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extern void get_dbat0(struct block_address_translation *bat);
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extern void get_dbat1(struct block_address_translation *bat);
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extern void get_dbat2(struct block_address_translation *bat);
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extern void get_dbat3(struct block_address_translation *bat);
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extern void reset_ibats(void);
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extern void reset_dbats(void);
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//extern void sethid0(unsigned int val);
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//extern unsigned int getl2cr(void);
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//extern void setl2cr(unsigned int val);
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extern long long get_time_base(void);
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void __ppc_setup_system_time(vint32 *cvFactor);
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// defined in libroot: os/arch/system_time.c
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int64 __ppc_get_time_base(void);
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// defined in libroot: os/arch/system_time_asm.S
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extern void ppc_context_switch(void **_oldStackPointer, void *newStackPointer);
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#ifdef __cplusplus
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}
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#endif
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#define eieio() asm volatile("eieio")
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#define isync() asm volatile("isync")
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#define tlbsync() asm volatile("tlbsync")
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#define ppc_sync() asm volatile("sync")
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#define tlbia() asm volatile("tlbia")
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#define tlbie(addr) asm volatile("tlbie %0" :: "r" (addr))
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// PowerPC processor version (the upper 16 bits of the PVR).
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enum ppc_processor_version {
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MPC601 = 0x0001,
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MPC603 = 0x0003,
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MPC604 = 0x0004,
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MPC602 = 0x0005,
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MPC603e = 0x0006,
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MPC603ev = 0x0007,
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MPC750 = 0x0008,
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MPC604ev = 0x0009,
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MPC7400 = 0x000c,
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MPC620 = 0x0014,
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IBM403 = 0x0020,
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IBM401A1 = 0x0021,
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IBM401B2 = 0x0022,
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IBM401C2 = 0x0023,
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IBM401D2 = 0x0024,
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IBM401E2 = 0x0025,
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IBM401F2 = 0x0026,
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IBM401G2 = 0x0027,
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IBMPOWER3 = 0x0041,
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MPC860 = 0x0050,
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MPC8240 = 0x0081,
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IBM405GP = 0x4011,
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IBM405L = 0x4161,
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IBM750FX = 0x7000,
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MPC7450 = 0x8000,
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MPC7455 = 0x8001,
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MPC7457 = 0x8002,
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MPC7447A = 0x8003,
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MPC7448 = 0x8004,
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MPC7410 = 0x800c,
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MPC8245 = 0x8081,
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};
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/*
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Use of (some) special purpose registers.
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SPRG0: per CPU physical address pointer to an ppc_cpu_exception_context
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structure
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SPRG1: scratch
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SPRG2: current struct thread*
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SPRG3: TLS base pointer (only for userland threads)
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*/
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#endif /* _KERNEL_ARCH_PPC_CPU_H */
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