updated register defines with info obtained from unichrome.sf.net.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@13716 a95241bf-73f2-0310-859d-f6bbb57e9c96
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@ -1,5 +1,7 @@
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/* registers definitions and macros for access to them */
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/* documentation can be found at http://unichrome.sourceforge.net/ */
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/* PCI_config_space */
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#define ENCFG_DEVID 0x00
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#define ENCFG_DEVCTRL 0x04
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@ -573,21 +575,12 @@
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#define ENCRTCX_MODECTL 0x17
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#define ENCRTCX_LINECOMP 0x18
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/* VIA specific registers: */
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//testing:
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#define ENCRTCX_0x19 0x19
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#define ENCRTCX_0x1a 0x1a
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#define ENCRTCX_0x1b 0x1b
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#define ENCRTCX_0x1c 0x1c
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#define ENCRTCX_0x1d 0x1d
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#define ENCRTCX_0x1e 0x1e
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#define ENCRTCX_0x1f 0x1f
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//end testing.
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#define ENCRTCX_0x32 0x32
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#define ENCRTCX_0x33 0x33
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#define ENCRTCX_HTIMEXT1 0x33
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#define ENCRTCX_FBSTADDE 0x34
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#define ENCRTCX_PITCHH 0x35
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#define ENCRTCX_0x36 0x36 //b6,7 = DPMS, 00 = on, 11=off
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#define ENCRTCX_0x3b 0x3b //TVtype jumper: b1=1 = PAL, else NTSC
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#define ENCRTCX_VTIMEXT_PIT 0x35
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#define ENCRTCX_HTIMEXT2 0x36 //b6,7 = DPMS, 00 = on, 11=off (4H,5V?)
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#define ENCRTCX_TVTYPE 0x3b //TVtype jumper: b1=1 = PAL, else NTSC
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//end via
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/* Nvidia specific registers: */
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#define ENCRTCX_REPAINT0 0x19
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