completed VIA CRTC timing programming. Updated internal constraints check, gettimingconstraints hook, and programming the crtc1. resolution can now be switched, but still excluding refresh programming (ie 640 to 800 switch turns off screen, but 800 to 640 switch just increases refresh from 60 to about 90 Hz (and apart from that works. :)
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@13715 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
parent
a00d33c094
commit
0204fda9d6
@ -1,6 +1,6 @@
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/*
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Author:
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Rudolf Cornelissen 7/2004
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Rudolf Cornelissen 7/2005
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*/
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#define MODULE_BIT 0x01000000
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@ -12,7 +12,7 @@ status_t GET_TIMING_CONSTRAINTS(display_timing_constraints * dtc)
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{
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LOG(4, ("GET_TIMING_CONSTRAINTS: returning info\n"));
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/* specs are identical for all nVidia cards */
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/* specs are identical for all VIA cards */
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dtc->h_res = 8;
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dtc->h_sync_min = 8;
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dtc->h_sync_max = 248;
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@ -21,7 +21,7 @@ status_t eng_crtc_validate_timing(
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*ht &= 0xfff8;
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/* confine to required number of bits, taking logic into account */
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if (*hd_e > ((0x01ff - 2) << 3)) *hd_e = ((0x01ff - 2) << 3);
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if (*hd_e > ((0x00ff - 2) << 3)) *hd_e = ((0x00ff - 2) << 3);
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if (*hs_s > ((0x01ff - 1) << 3)) *hs_s = ((0x01ff - 1) << 3);
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if (*hs_e > ( 0x01ff << 3)) *hs_e = ( 0x01ff << 3);
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if (*ht > ((0x01ff + 5) << 3)) *ht = ((0x01ff + 5) << 3);
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@ -29,14 +29,9 @@ status_t eng_crtc_validate_timing(
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/* NOTE: keep horizontal timing at multiples of 8! */
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/* confine to a reasonable width */
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if (*hd_e < 640) *hd_e = 640;
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if (si->ps.card_type > NV04)
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{
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if (*hd_e > 2048) *hd_e = 2048;
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}
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else
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{
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if (*hd_e > 1920) *hd_e = 1920;
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}
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/* assuming all VIA unichrome cards to have same max. constraint.. */
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//fixme: checkout correct max...
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if (*hd_e > 1600) *hd_e = 1600;
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/* if hor. total does not leave room for a sensible sync pulse, increase it! */
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if (*ht < (*hd_e + 80)) *ht = (*hd_e + 80);
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@ -54,7 +49,6 @@ status_t eng_crtc_validate_timing(
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/*vertical*/
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/* confine to required number of bits, taking logic into account */
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//fixme if needed: on GeForce cards there are 12 instead of 11 bits...
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if (*vd_e > (0x7ff - 2)) *vd_e = (0x7ff - 2);
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if (*vs_s > (0x7ff - 1)) *vs_s = (0x7ff - 1);
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if (*vs_e > 0x7ff ) *vs_e = 0x7ff ;
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@ -62,14 +56,9 @@ status_t eng_crtc_validate_timing(
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/* confine to a reasonable height */
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if (*vd_e < 480) *vd_e = 480;
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if (si->ps.card_type > NV04)
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{
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if (*vd_e > 1536) *vd_e = 1536;
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}
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else
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{
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if (*vd_e > 1440) *vd_e = 1440;
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}
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/* assuming all VIA unichrome cards to have same max. constraint.. */
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//fixme: checkout correct max...
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if (*vd_e > 1200) *vd_e = 1200;
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/*if vertical total does not leave room for a sync pulse, increase it!*/
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if (*vt < (*vd_e + 3)) *vt = (*vd_e + 3);
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@ -190,8 +179,9 @@ status_t eng_crtc_set_timing(display_mode target)
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vsync_s = target.timing.v_sync_start;//-1;
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vsync_e = target.timing.v_sync_end;//-1;
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/* prevent memory adress counter from being reset (linecomp may not occur) */
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linecomp = target.timing.v_display;
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/* prevent memory adress counter from being reset (linecomp may not occur).
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* set all bits, otherwise distortion stripes may appear onscreen (VIA) */
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linecomp = 0xffff;
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/* Note for laptop and DVI flatpanels:
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* CRTC timing has a seperate set of registers from flatpanel timing.
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@ -223,10 +213,10 @@ status_t eng_crtc_set_timing(display_mode target)
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((vtotal & 0x100) >> (8 - 0)) | ((vtotal & 0x200) >> (9 - 5)) |
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((vdisp_e & 0x100) >> (8 - 1)) | ((vdisp_e & 0x200) >> (9 - 6)) |
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((vsync_s & 0x100) >> (8 - 2)) | ((vsync_s & 0x200) >> (9 - 7)) |
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((vblnk_s & 0x100) >> (8 - 3)) | ((linecomp & 0x100) >> (8 - 4))
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((vblnk_s & 0x100) >> (8 - 3)) | ((linecomp & 0x0100) >> (8 - 4))
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));
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CRTCW(PRROWSCN, 0x00); /* not used */
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CRTCW(MAXSCLIN, (((vblnk_s & 0x200) >> (9 - 5)) | ((linecomp & 0x200) >> (9 - 6))));
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CRTCW(MAXSCLIN, (((vblnk_s & 0x200) >> (9 - 5)) | ((linecomp & 0x0200) >> (9 - 6))));
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CRTCW(VSYNCS, (vsync_s & 0xff));
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CRTCW(VSYNCE, ((CRTCR(VSYNCE) & 0xf0) | (vsync_e & 0x0f)));
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CRTCW(VDISPE, (vdisp_e & 0xff));
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@ -235,46 +225,23 @@ status_t eng_crtc_set_timing(display_mode target)
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CRTCW(LINECOMP, (linecomp & 0xff));
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/* horizontal extended regs */
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//fixme: we reset bit4. is this correct??
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/* CRTCW(HEB, (CRTCR(HEB) & 0xe0) |
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CRTCW(HTIMEXT1, (CRTCR(HTIMEXT1) & 0xc8) |
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(
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((htotal & 0x100) >> (8 - 0)) |
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((hdisp_e & 0x100) >> (8 - 1)) |
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((hblnk_s & 0x100) >> (8 - 2)) |
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((hsync_s & 0x100) >> (8 - 3))
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((linecomp & 0x1c00) >> (10 - 0)) |
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((hblnk_e & 0x040) >> (6 - 5)) |
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((hsync_s & 0x100) >> (8 - 4))
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));
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*/
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/* (mostly) vertical extended regs */
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/* CRTCW(LSR,
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CRTCW(HTIMEXT2, (CRTCR(HTIMEXT2) & 0xf7) | ((htotal & 0x100) >> (8 - 3)));
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/* vertical extended regs */
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CRTCW(VTIMEXT_PIT, (CRTCR(VTIMEXT_PIT) & 0xe0) |
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(
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((vtotal & 0x400) >> (10 - 0)) |
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((vdisp_e & 0x400) >> (10 - 1)) |
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((vsync_s & 0x400) >> (10 - 2)) |
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((vsync_s & 0x400) >> (10 - 1)) |
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((vdisp_e & 0x400) >> (10 - 2)) |
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((vblnk_s & 0x400) >> (10 - 3)) |
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((hblnk_e & 0x040) >> (6 - 4))
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//fixme: we still miss one linecomp bit!?! is this it??
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//| ((linecomp & 0x400) >> 3)
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((linecomp & 0x2000) >> (13 - 4))
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));
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*/
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/* more vertical extended regs (on GeForce cards only) */
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/*
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if (si->ps.card_arch >= NV10A)
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{
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CRTCW(EXTRA,
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(
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((vtotal & 0x800) >> (11 - 0)) |
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((vdisp_e & 0x800) >> (11 - 2)) |
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((vsync_s & 0x800) >> (11 - 4)) |
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((vblnk_s & 0x800) >> (11 - 6))
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//fixme: do we miss another linecomp bit!?!
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));
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}
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*/
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/* setup 'large screen' mode */
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// if (target.timing.h_display >= 1280)
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// CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0xfb));
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// else
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// CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x04));
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/* setup HSYNC & VSYNC polarity */
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LOG(2,("CRTC: sync polarity: "));
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@ -587,7 +554,7 @@ status_t eng_crtc_set_display_pitch()
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/* program the card */
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CRTCW(PITCHL, (offset & 0x00ff));
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CRTCW(PITCHH, (((CRTCR(PITCHH)) & 0x1f) | ((offset & 0x0700) >> 3)));
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CRTCW(VTIMEXT_PIT, (((CRTCR(VTIMEXT_PIT)) & 0x1f) | ((offset & 0x0700) >> 3)));
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//test stuff:
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// LOG(2,("CRTC: $32=$%02x, $33=$%02x, $35=$%02x, $36=$%02x\n",
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