setup hardware cursor. bitmap not yet correct, colors neither.

git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@13634 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen 2005-07-11 15:30:18 +00:00
parent 5de64e32fd
commit f1971991da

View File

@ -143,34 +143,34 @@ static void dumprom (void *rom, uint32 size)
/* return 1 if vblank interrupt has occured */ /* return 1 if vblank interrupt has occured */
static int caused_vbi(vuint32 * regs) static int caused_vbi(vuint32 * regs)
{ {
// return (ENG_RG32(RG32_CRTC_INTS) & 0x00000001); // return (ENG_REG32(RG32_CRTC_INTS) & 0x00000001);
return 0; return 0;
} }
/* clear the vblank interrupt */ /* clear the vblank interrupt */
static void clear_vbi(vuint32 * regs) static void clear_vbi(vuint32 * regs)
{ {
// ENG_RG32(RG32_CRTC_INTS) = 0x00000001; // ENG_REG32(RG32_CRTC_INTS) = 0x00000001;
} }
static void enable_vbi(vuint32 * regs) static void enable_vbi(vuint32 * regs)
{ {
/* clear the vblank interrupt */ /* clear the vblank interrupt */
// ENG_RG32(RG32_CRTC_INTS) = 0x00000001; // ENG_REG32(RG32_CRTC_INTS) = 0x00000001;
/* enable nVidia interrupt source vblank */ /* enable nVidia interrupt source vblank */
// ENG_RG32(RG32_CRTC_INTE) |= 0x00000001; // ENG_REG32(RG32_CRTC_INTE) |= 0x00000001;
/* enable nVidia interrupt system hardware (b0-1) */ /* enable nVidia interrupt system hardware (b0-1) */
// ENG_RG32(RG32_MAIN_INTE) = 0x00000001; // ENG_REG32(RG32_MAIN_INTE) = 0x00000001;
} }
static void disable_vbi(vuint32 * regs) static void disable_vbi(vuint32 * regs)
{ {
/* disable nVidia interrupt source vblank */ /* disable nVidia interrupt source vblank */
// ENG_RG32(RG32_CRTC_INTE) &= 0xfffffffe; // ENG_REG32(RG32_CRTC_INTE) &= 0xfffffffe;
/* clear the vblank interrupt */ /* clear the vblank interrupt */
// ENG_RG32(RG32_CRTC_INTS) = 0x00000001; // ENG_REG32(RG32_CRTC_INTS) = 0x00000001;
/* disable nVidia interrupt system hardware (b0-1) */ /* disable nVidia interrupt system hardware (b0-1) */
// ENG_RG32(RG32_MAIN_INTE) = 0x00000000; // ENG_REG32(RG32_MAIN_INTE) = 0x00000000;
} }
/* /*