setup hardware cursor. bitmap not yet correct, colors neither.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@13633 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
parent
9784ce8df4
commit
5de64e32fd
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@ -4,7 +4,7 @@
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Other authors:
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Mark Watson,
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Rudolf Cornelissen 10/2002-4/2004
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Rudolf Cornelissen 10/2002-7/2005
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*/
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#define MODULE_BIT 0x08000000
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@ -4,7 +4,7 @@
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Other authors:
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Mark Watson,
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Rudolf Cornelissen 10/2002-7/2004.
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Rudolf Cornelissen 10/2002-7/2005.
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*/
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#define MODULE_BIT 0x00800000
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@ -153,8 +153,9 @@ status_t INIT_ACCELERANT(int the_fd) {
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to the app_server later.
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*/
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pointer_reservation = 0;
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/* Nvidia hardcursor needs 2kB space */
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if (si->settings.hardcursor) pointer_reservation = 2048;
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/* VIA hardcursor needs 4kB space */
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//rud: shutoff until adress of FB is programmed! <<<<<<<<<<
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// if (si->settings.hardcursor) pointer_reservation = 4096;
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si->fbc.frame_buffer = (void *)((char *)si->framebuffer+pointer_reservation);
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si->fbc.frame_buffer_dma = (void *)((char *)si->framebuffer_pci+pointer_reservation);
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@ -25,15 +25,15 @@ status_t eng_agp_setup(void)
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// {
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// uint32 reg;
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// LOG(4, ("AGP: STRAPINFO2 contains $%08x\n", ENG_RG32(RG32_NVSTRAPINFO2)));
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// LOG(4, ("AGP: STRAPINFO2 contains $%08x\n", ENG_REG32(RG32_NVSTRAPINFO2)));
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// LOG(4, ("AGP: attempting to enable fastwrite support..\n"));
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/* 'force' FW support */
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// reg = (ENG_RG32(RG32_NVSTRAPINFO2) & ~0x00000800);
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// reg = (ENG_REG32(RG32_NVSTRAPINFO2) & ~0x00000800);
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/* enable strapinfo overwrite */
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// ENG_RG32(RG32_NVSTRAPINFO2) = (reg | 0x80000000);
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// ENG_REG32(RG32_NVSTRAPINFO2) = (reg | 0x80000000);
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// LOG(4, ("AGP: STRAPINFO2 now contains $%08x\n", ENG_RG32(RG32_NVSTRAPINFO2)));
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// LOG(4, ("AGP: STRAPINFO2 now contains $%08x\n", ENG_REG32(RG32_NVSTRAPINFO2)));
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// }
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/* set the magic number so the skeleton kerneldriver knows we're for real */
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@ -357,16 +357,16 @@ status_t eng_bes_to_crtc(bool crtc)
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{
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LOG(4,("Overlay: switching overlay to CRTC2\n"));
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/* switch overlay engine to CRTC2 */
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ENG_RG32(RG32_FUNCSEL) &= ~0x00001000;
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ENG_RG32(RG32_2FUNCSEL) |= 0x00001000;
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ENG_REG32(RG32_FUNCSEL) &= ~0x00001000;
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ENG_REG32(RG32_2FUNCSEL) |= 0x00001000;
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si->overlay.crtc = !si->crtc_switch_mode;
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}
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else
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{
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LOG(4,("Overlay: switching overlay to CRTC1\n"));
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/* switch overlay engine to CRTC1 */
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ENG_RG32(RG32_2FUNCSEL) &= ~0x00001000;
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ENG_RG32(RG32_FUNCSEL) |= 0x00001000;
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ENG_REG32(RG32_2FUNCSEL) &= ~0x00001000;
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ENG_REG32(RG32_FUNCSEL) |= 0x00001000;
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si->overlay.crtc = si->crtc_switch_mode;
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}
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return B_OK;
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@ -1,6 +1,6 @@
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/* CTRC functionality */
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/* Author:
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Rudolf Cornelissen 11/2002-9/2004
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Rudolf Cornelissen 11/2002-7/2005
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*/
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#define MODULE_BIT 0x00040000
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@ -610,7 +610,7 @@ status_t eng_crtc_set_display_start(uint32 startadd,uint8 bpp)
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/* we might have no retraces during setmode! */
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/* wait 25mS max. for retrace to occur (refresh > 40Hz) */
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while (((ENG_RG32(RG32_RASTER) & 0x000007ff) < si->dm.timing.v_display) &&
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while (((ENG_REG32(RG32_RASTER) & 0x000007ff) < si->dm.timing.v_display) &&
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(timeout < (25000/10)))
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{
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/* don't snooze much longer or retrace might get missed! */
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@ -646,7 +646,7 @@ status_t eng_crtc_set_display_start(uint32 startadd,uint8 bpp)
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* wrap-around at 16Mb boundaries!! */
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/* 30bit adress in 32bit words */
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ENG_RG32(RG32_NV10FBSTADD32) = (startadd & 0xfffffffc);
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ENG_REG32(RG32_NV10FBSTADD32) = (startadd & 0xfffffffc);
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}
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/* set NV4/NV10 byte adress: (b0 - 1) */
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@ -662,11 +662,8 @@ status_t eng_crtc_cursor_init()
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/* cursor bitmap will be stored at the start of the framebuffer */
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const uint32 curadd = 0;
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/* enable access to primary head */
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set_crtc_owner(0);
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/* set cursor bitmap adress ... */
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if ((si->ps.card_arch == NV04A) || (si->ps.laptop))
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if (0)//(si->ps.card_arch == NV04A) || (si->ps.laptop))
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{
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/* must be used this way on pre-NV10 and on all 'Go' cards! */
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@ -686,20 +683,24 @@ status_t eng_crtc_cursor_init()
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* This register does not exist on pre-NV10 and 'Go' cards. */
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/* cursorbitmap must still start on 2Kbyte boundary: */
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ENG_RG32(RG32_NV10CURADD32) = (curadd & 0xfffff800);
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//via
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/* background is black */
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CRTCDW(CURSOR_BG, 0x00000000);
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/* foreground is white */
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CRTCDW(CURSOR_FG, 0x00ffffff);
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/* set cursor bitmap adress */
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CRTCDW(CURSOR_MODE, (curadd & 0xfffffffc));
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}
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/* set cursor colour: not needed because of direct nature of cursor bitmap. */
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/*clear cursor*/
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/* clear cursor (via cursor uses 4kb) */
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fb = (uint32 *) si->framebuffer + curadd;
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for (i=0;i<(2048/4);i++)
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for (i=0;i<(4096/4);i++)
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{
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fb[i]=0;
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}
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/* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */
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ENG_RG32(RG32_CURCONF) = 0x02000100;
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// ENG_REG32(RG32_CURCONF) = 0x02000100;
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/* activate hardware cursor */
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eng_crtc_cursor_show();
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@ -710,12 +711,7 @@ status_t eng_crtc_cursor_init()
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status_t eng_crtc_cursor_show()
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{
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LOG(4,("CRTC: enabling cursor\n"));
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/* enable access to CRTC1 on dualhead cards */
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set_crtc_owner(0);
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/* b0 = 1 enables cursor */
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CRTCW(CURCTL0, (CRTCR(CURCTL0) | 0x01));
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CRTCDW(CURSOR_MODE, (CRTCDR(CURSOR_MODE) | 0x00000003));
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return B_OK;
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}
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@ -723,12 +719,7 @@ status_t eng_crtc_cursor_show()
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status_t eng_crtc_cursor_hide()
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{
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LOG(4,("CRTC: disabling cursor\n"));
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/* enable access to primary head */
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set_crtc_owner(0);
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/* b0 = 0 disables cursor */
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CRTCW(CURCTL0, (CRTCR(CURCTL0) & 0xfe));
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CRTCDW(CURSOR_MODE, (CRTCDR(CURSOR_MODE) & 0xfffffffc));
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return B_OK;
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}
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@ -736,50 +727,50 @@ status_t eng_crtc_cursor_hide()
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/*set up cursor shape*/
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status_t eng_crtc_cursor_define(uint8* andMask,uint8* xorMask)
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{
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int x, y;
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uint8 b;
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int y;
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uint8 b,s;
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uint16 *cursor;
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uint16 pixel;
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uint16 data;
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/* get a pointer to the cursor */
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cursor = (uint16*) si->framebuffer;
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/* draw the cursor */
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/* (Nvidia cards have a RGB15 direct color cursor bitmap, bit #16 is transparancy) */
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for (y = 0; y < 16; y++)
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{
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b = 0x80;
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for (x = 0; x < 8; x++)
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b = 0x01;
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/* preset transparant */
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data = 0x0000;
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for (s = 0; s < 15; s += 2)
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{
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/* preset transparant */
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pixel = 0x0000;
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/* set white if requested */
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if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff;
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if ((!(*andMask & b)) && (!(*xorMask & b))) data |= (0x0003 << s);
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/* set black if requested */
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if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000;
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if ((!(*andMask & b)) && (*xorMask & b)) data |= (0x0002 << s);
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/* set invert if requested */
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if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff;
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/* place the pixel in the bitmap */
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cursor[x + (y * 32)] = pixel;
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b >>= 1;
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if ( (*andMask & b) && (*xorMask & b)) data |= (0x0001 << s);
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b <<= 1;
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}
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/* place the 8 pixels in the bitmap */
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cursor[0 + (y * 4)] = data;
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xorMask++;
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andMask++;
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b = 0x80;
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for (; x < 16; x++)
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b = 0x01;
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/* preset transparant */
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data = 0x0000;
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for (s = 0; s < 15; s += 2)
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{
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/* preset transparant */
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pixel = 0x0000;
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/* set white if requested */
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if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff;
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if ((!(*andMask & b)) && (!(*xorMask & b))) data |= (0x0003 << s);
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/* set black if requested */
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if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000;
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if ((!(*andMask & b)) && (*xorMask & b)) data |= (0x0002 << s);
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/* set invert if requested */
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if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff;
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/* place the pixel in the bitmap */
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cursor[x + (y * 32)] = pixel;
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b >>= 1;
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if ( (*andMask & b) && (*xorMask & b)) data |= (0x0001 << s);
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b <<= 1;
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}
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/* place the 8 pixels in the bitmap */
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cursor[1 + (y * 4)] = data;
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xorMask++;
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andMask++;
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}
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@ -790,40 +781,11 @@ status_t eng_crtc_cursor_define(uint8* andMask,uint8* xorMask)
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/* position the cursor */
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status_t eng_crtc_cursor_position(uint16 x, uint16 y)
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{
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uint16 yhigh;
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/* make sure we are beyond the first line of the cursorbitmap being drawn during
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* updating the position to prevent distortions: no double buffering feature */
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/* Note:
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* we need to return as quick as possible or some apps will exhibit lagging.. */
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/* read the old cursor Y position */
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yhigh = ((DACR(CURPOS) & 0x0fff0000) >> 16);
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/* make sure we will wait until we are below both the old and new Y position:
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* visible cursorbitmap drawing needs to be done at least... */
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if (y > yhigh) yhigh = y;
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if (yhigh < (si->dm.timing.v_display - 16))
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{
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/* we have vertical lines below old and new cursorposition to spare. So we
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* update the cursor postion 'mid-screen', but below that area. */
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while (((uint16)(ENG_RG32(RG32_RASTER) & 0x000007ff)) < (yhigh + 16))
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{
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snooze(10);
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}
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}
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else
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{
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/* no room to spare, just wait for retrace (is relatively slow) */
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while ((ENG_RG32(RG32_RASTER) & 0x000007ff) < si->dm.timing.v_display)
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{
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/* don't snooze much longer or retrace might get missed! */
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snooze(10);
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}
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}
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/* set cursor origin, b1-7 = Y offset; b17-23 = X offset
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* (? linux seems non-consistent) */
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CRTCDW(CURSOR_ORG, 0x00000000);
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/* update cursorposition */
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DACW(CURPOS, ((x & 0x0fff) | ((y & 0x0fff) << 16)));
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CRTCDW(CURSOR_POS, (((x & 0x07ff) << 16) | (y & 0x07ff)));
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return B_OK;
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}
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@ -592,7 +592,7 @@ status_t eng_crtc2_set_display_start(uint32 startadd,uint8 bpp)
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/* we might have no retraces during setmode! */
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/* wait 25mS max. for retrace to occur (refresh > 40Hz) */
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while (((ENG_RG32(RG32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) &&
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while (((ENG_REG32(RG32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) &&
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(timeout < (25000/10)))
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{
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/* don't snooze much longer or retrace might get missed! */
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@ -609,7 +609,7 @@ status_t eng_crtc2_set_display_start(uint32 startadd,uint8 bpp)
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* wrap-around at 16Mb boundaries!! */
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/* 30bit adress in 32bit words */
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ENG_RG32(RG32_NV10FB2STADD32) = (startadd & 0xfffffffc);
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ENG_REG32(RG32_NV10FB2STADD32) = (startadd & 0xfffffffc);
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/* set byte adress: (b0 - 1) */
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ATB2W(HORPIXPAN, ((startadd & 0x00000003) << 1));
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@ -648,7 +648,7 @@ status_t eng_crtc2_cursor_init()
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* This register does not exist on pre-NV10 and 'Go' cards. */
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/* cursorbitmap must still start on 2Kbyte boundary: */
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ENG_RG32(RG32_NV10CUR2ADD32) = (curadd & 0xfffff800);
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ENG_REG32(RG32_NV10CUR2ADD32) = (curadd & 0xfffff800);
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}
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/* set cursor colour: not needed because of direct nature of cursor bitmap. */
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@ -661,7 +661,7 @@ status_t eng_crtc2_cursor_init()
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}
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/* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */
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ENG_RG32(RG32_2CURCONF) = 0x02000100;
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ENG_REG32(RG32_2CURCONF) = 0x02000100;
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/* activate hardware cursor */
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eng_crtc2_cursor_show();
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@ -769,7 +769,7 @@ status_t eng_crtc2_cursor_position(uint16 x, uint16 y)
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{
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/* we have vertical lines below old and new cursorposition to spare. So we
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* update the cursor postion 'mid-screen', but below that area. */
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while (((uint16)(ENG_RG32(RG32_RASTER2) & 0x000007ff)) < (yhigh + 16))
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while (((uint16)(ENG_REG32(RG32_RASTER2) & 0x000007ff)) < (yhigh + 16))
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{
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snooze(10);
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}
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@ -777,7 +777,7 @@ status_t eng_crtc2_cursor_position(uint16 x, uint16 y)
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else
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{
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/* no room to spare, just wait for retrace (is relatively slow) */
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while ((ENG_RG32(RG32_RASTER2) & 0x000007ff) < si->dm.timing.v_display)
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while ((ENG_REG32(RG32_RASTER2) & 0x000007ff) < si->dm.timing.v_display)
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{
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/* don't snooze much longer or retrace might get missed! */
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snooze(10);
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@ -90,7 +90,7 @@ status_t eng_general_powerup()
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{
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status_t status;
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LOG(1,("POWERUP: Haiku skeleton Accelerant 0.01 running.\n"));
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LOG(1,("POWERUP: Haiku VIA Accelerant 0.01 running.\n"));
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/* preset no laptop */
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si->ps.laptop = false;
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@ -102,7 +102,7 @@ status_t eng_general_powerup()
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case 0x31221106: /* */
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si->ps.card_type = NV04;
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si->ps.card_arch = NV04A;
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LOG(4,("POWERUP: Detected Nvidia TNT1 (NV04)\n"));
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LOG(4,("POWERUP: Detected VIA CLE266 Unichrome\n"));
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status = engxx_general_powerup();
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break;
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default:
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@ -416,7 +416,7 @@ status_t eng_general_head_select(bool cross)
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static status_t eng_general_bios_to_powergraphics()
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{
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/* let acc engine make power off/power on cycle to start 'fresh' */
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// ENG_RG32(RG32_PWRUPCTRL) = 0x13110011;
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// ENG_REG32(RG32_PWRUPCTRL) = 0x13110011;
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snooze(1000);
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/* power-up all hardware function blocks */
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@ -429,7 +429,7 @@ static status_t eng_general_bios_to_powergraphics()
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* bit 8: PFIFO,
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* bit 4: PMEDIA,
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* bit 0: TVOUT. (> NV04A) */
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// ENG_RG32(RG32_PWRUPCTRL) = 0x13111111;
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// ENG_REG32(RG32_PWRUPCTRL) = 0x13111111;
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/* select colormode CRTC registers base adresses */
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// ENG_REG8(RG8_MISCW) = 0xcb;
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@ -469,8 +469,8 @@ static status_t eng_general_bios_to_powergraphics()
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* bit 9: TVout chip #2 (confirmed on NV18, NV25, NV28),
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* bit 8: TVout chip #1 (all cards),
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* bit 4: both I2C busses (all cards) */
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ENG_RG32(RG32_2FUNCSEL) &= ~0x00001000;
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ENG_RG32(RG32_FUNCSEL) |= 0x00001000;
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ENG_REG32(RG32_2FUNCSEL) &= ~0x00001000;
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ENG_REG32(RG32_FUNCSEL) |= 0x00001000;
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}
|
||||
si->overlay.crtc = false;
|
||||
|
||||
|
|
|
|||
|
|
@ -311,8 +311,8 @@ static status_t coldstart_card_516_up(uint8* rom, PinsTables tabs, uint16 ram_ta
|
|||
//fixme?: works on at least one NV28... how about other cards?
|
||||
if (si->ps.card_type == NV28)
|
||||
{
|
||||
fb_mrs2 = ENG_RG32(RG32_FB_MRS2);
|
||||
fb_mrs1 = ENG_RG32(RG32_FB_MRS1);
|
||||
fb_mrs2 = ENG_REG32(RG32_FB_MRS2);
|
||||
fb_mrs1 = ENG_REG32(RG32_FB_MRS1);
|
||||
}
|
||||
|
||||
/* select colormode CRTC registers base adresses */
|
||||
|
|
@ -381,8 +381,8 @@ static status_t coldstart_card_516_up(uint8* rom, PinsTables tabs, uint16 ram_ta
|
|||
|
||||
/* get NV28 RAM access up and running */
|
||||
//fixme?: works on at least one NV28... how about other cards?
|
||||
ENG_RG32(RG32_FB_MRS2) = fb_mrs2;
|
||||
ENG_RG32(RG32_FB_MRS1) = fb_mrs1;
|
||||
ENG_REG32(RG32_FB_MRS2) = fb_mrs2;
|
||||
ENG_REG32(RG32_FB_MRS1) = fb_mrs1;
|
||||
}
|
||||
|
||||
/* now enable ROM shadow or the card will remain shut-off! */
|
||||
|
|
@ -448,7 +448,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
|
|||
float calced_clk;
|
||||
uint8 m, n, p;
|
||||
eng_dac_sys_pll_find(((float)data2), &calced_clk, &m, &n, &p, 0);
|
||||
ENG_RG32(reg) = ((p << 16) | (n << 8) | m);
|
||||
ENG_REG32(reg) = ((p << 16) | (n << 8) | m);
|
||||
}
|
||||
log_pll(reg, data2);
|
||||
break;
|
||||
|
|
@ -470,7 +470,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
|
|||
adress += 2;
|
||||
data2 = *((uint32*)(&(rom[data])));
|
||||
LOG(8,("cmd 'WR indirect 32bit reg' $%08x = $%08x\n", reg, data2));
|
||||
if (exec) ENG_RG32(reg) = data2;
|
||||
if (exec) ENG_REG32(reg) = data2;
|
||||
break;
|
||||
case 0x63:
|
||||
*size -= 1;
|
||||
|
|
@ -509,8 +509,8 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
|
|||
LOG(8,("cmd 'WR 32bit reg $%08x = $%08x, then = $%08x' (always done)\n",
|
||||
reg, data, data2));
|
||||
/* always done */
|
||||
ENG_RG32(reg) = data;
|
||||
ENG_RG32(reg) = data2;
|
||||
ENG_REG32(reg) = data;
|
||||
ENG_REG32(reg) = data2;
|
||||
CFGW(ROMSHADOW, (CFGR(ROMSHADOW) & 0xfffffffe));
|
||||
break;
|
||||
case 0x69:
|
||||
|
|
@ -554,7 +554,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
|
|||
|
||||
/* execute */
|
||||
adress += 1;
|
||||
data = ENG_RG32(RG32_NV4STRAPINFO);
|
||||
data = ENG_REG32(RG32_NV4STRAPINFO);
|
||||
and_out = *((uint8*)(&(rom[adress])));
|
||||
adress += 1;
|
||||
byte = *((uint8*)(&(rom[adress])));
|
||||
|
|
@ -594,10 +594,10 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
|
|||
reg, and_out, or_in));
|
||||
if (exec)
|
||||
{
|
||||
data = ENG_RG32(reg);
|
||||
data = ENG_REG32(reg);
|
||||
data &= and_out;
|
||||
data |= or_in;
|
||||
ENG_RG32(reg) = data;
|
||||
ENG_REG32(reg) = data;
|
||||
}
|
||||
break;
|
||||
case 0x71:
|
||||
|
|
@ -637,7 +637,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
|
|||
|
||||
/* execute */
|
||||
adress += 1;
|
||||
data = ENG_RG32(RG32_NVSTRAPINFO2);
|
||||
data = ENG_REG32(RG32_NVSTRAPINFO2);
|
||||
and_out = *((uint32*)(&(rom[adress])));
|
||||
adress += 4;
|
||||
data2 = *((uint32*)(&(rom[adress])));
|
||||
|
|
@ -691,7 +691,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
|
|||
adress += 2;
|
||||
LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x (b31-16 = '0', b15-0 = data)\n",
|
||||
reg, data));
|
||||
if (exec) ENG_RG32(reg) = data;
|
||||
if (exec) ENG_REG32(reg) = data;
|
||||
break;
|
||||
case 0x78:
|
||||
*size -= 6;
|
||||
|
|
@ -747,7 +747,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
|
|||
float calced_clk;
|
||||
uint8 m, n, p;
|
||||
eng_dac_sys_pll_find((data / 100.0), &calced_clk, &m, &n, &p, 0);
|
||||
ENG_RG32(reg) = ((p << 16) | (n << 8) | m);
|
||||
ENG_REG32(reg) = ((p << 16) | (n << 8) | m);
|
||||
}
|
||||
log_pll(reg, (data / 100));
|
||||
break;
|
||||
|
|
@ -768,7 +768,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
|
|||
data = *((uint32*)(&(rom[adress])));
|
||||
adress += 4;
|
||||
LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x\n", reg, data));
|
||||
if (exec) ENG_RG32(reg) = data;
|
||||
if (exec) ENG_REG32(reg) = data;
|
||||
break;
|
||||
default:
|
||||
LOG(8,("unknown cmd, aborting!\n\n"));
|
||||
|
|
@ -828,9 +828,9 @@ static void setup_ram_config(uint8* rom, uint16 ram_tab)
|
|||
uint8 cnt;
|
||||
|
||||
/* set MRS = 256 */
|
||||
ENG_RG32(RG32_PFB_DEBUG_0) &= 0xffffffef;
|
||||
ENG_REG32(RG32_PFB_DEBUG_0) &= 0xffffffef;
|
||||
/* read RAM config hardware(?) strap */
|
||||
ram_cfg = ((ENG_RG32(RG32_NVSTRAPINFO2) >> 2) & 0x0000000f);
|
||||
ram_cfg = ((ENG_REG32(RG32_NVSTRAPINFO2) >> 2) & 0x0000000f);
|
||||
LOG(8,("INFO: ---RAM config strap is $%01x\n", ram_cfg));
|
||||
/* use it as a pointer in a BIOS table for prerecorded RAM configurations */
|
||||
ram_cfg = *((uint16*)(&(rom[(ram_tab + (ram_cfg * 2))])));
|
||||
|
|
@ -876,15 +876,15 @@ static void setup_ram_config(uint8* rom, uint16 ram_tab)
|
|||
break;
|
||||
}
|
||||
/* set RAM amount, width and type */
|
||||
data = (ENG_RG32(RG32_NV4STRAPINFO) & 0xffffffc0);
|
||||
ENG_RG32(RG32_NV4STRAPINFO) = (data | (ram_cfg & 0x0000003f));
|
||||
data = (ENG_REG32(RG32_NV4STRAPINFO) & 0xffffffc0);
|
||||
ENG_REG32(RG32_NV4STRAPINFO) = (data | (ram_cfg & 0x0000003f));
|
||||
/* setup write to read delay (?) */
|
||||
data = (ENG_RG32(RG32_PFB_CONFIG_1) & 0xff8ffffe);
|
||||
data = (ENG_REG32(RG32_PFB_CONFIG_1) & 0xff8ffffe);
|
||||
data |= ((ram_cfg & 0x00000700) << 12);
|
||||
/* force update via b0 = 0... */
|
||||
ENG_RG32(RG32_PFB_CONFIG_1) = data;
|
||||
ENG_REG32(RG32_PFB_CONFIG_1) = data;
|
||||
/* ... followed by b0 = 1(?) */
|
||||
ENG_RG32(RG32_PFB_CONFIG_1) = (data | 0x00000001);
|
||||
ENG_REG32(RG32_PFB_CONFIG_1) = (data | 0x00000001);
|
||||
|
||||
/* do RAM width test to confirm RAM width set to be correct */
|
||||
/* write testpattern to first 128 bits of graphics memory... */
|
||||
|
|
@ -896,7 +896,7 @@ static void setup_ram_config(uint8* rom, uint16 ram_tab)
|
|||
if (((uint32 *)si->framebuffer)[3] != data)
|
||||
{
|
||||
LOG(8,("INFO: ---RAM width tested: width is 64bits, correcting settings.\n"));
|
||||
ENG_RG32(RG32_NV4STRAPINFO) &= ~0x00000004;
|
||||
ENG_REG32(RG32_NV4STRAPINFO) &= ~0x00000004;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -963,11 +963,11 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
|
|||
LOG(8,("INFO: (cont.) then WR result data to 32bit reg $%08x'\n", reg2));
|
||||
if (*exec && reg2)
|
||||
{
|
||||
data = ENG_RG32(reg);
|
||||
data = ENG_REG32(reg);
|
||||
data &= and_out;
|
||||
data >>= shift;
|
||||
data2 = *((uint32*)(&(rom[(*adress + (data << 2))])));
|
||||
ENG_RG32(reg2) = data2;
|
||||
ENG_REG32(reg2) = data2;
|
||||
}
|
||||
*adress += size32;
|
||||
break;
|
||||
|
|
@ -1009,7 +1009,7 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
|
|||
byte >>= byte2;
|
||||
offset32 = (byte << 2);
|
||||
data = *((uint32*)(&(rom[(*adress + offset32)])));
|
||||
ENG_RG32(reg2) = data;
|
||||
ENG_REG32(reg2) = data;
|
||||
}
|
||||
*adress += size32;
|
||||
break;
|
||||
|
|
@ -1102,10 +1102,10 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
|
|||
uint8 m, n, p;
|
||||
eng_dac_sys_pll_find((data2 / 100.0), &calced_clk, &m, &n, &p, 0);
|
||||
/* programming the PLL needs to be done in steps! (confirmed NV28) */
|
||||
data = ENG_RG32(reg2);
|
||||
ENG_RG32(reg2) = ((data & 0xffff0000) | (n << 8) | m);
|
||||
data = ENG_RG32(reg2);
|
||||
ENG_RG32(reg2) = ((p << 16) | (n << 8) | m);
|
||||
data = ENG_REG32(reg2);
|
||||
ENG_REG32(reg2) = ((data & 0xffff0000) | (n << 8) | m);
|
||||
data = ENG_REG32(reg2);
|
||||
ENG_REG32(reg2) = ((p << 16) | (n << 8) | m);
|
||||
//fixme?
|
||||
/* program 2nd set N and M scalers if they exist (b31=1 enables them) */
|
||||
// if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36))
|
||||
|
|
@ -1178,7 +1178,7 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
|
|||
index, reg2, and_out2));
|
||||
if (*exec)
|
||||
{
|
||||
data = ENG_RG32(reg);
|
||||
data = ENG_REG32(reg);
|
||||
if (byte2 < 0x80)
|
||||
{
|
||||
data >>= byte2;
|
||||
|
|
@ -1274,12 +1274,12 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
|
|||
*adress += 1;
|
||||
data2 = *((uint8*)(&(rom[*adress])));
|
||||
*adress += 1;
|
||||
ENG_RG32(reg2) = data2;
|
||||
data = ENG_RG32(reg);
|
||||
ENG_REG32(reg2) = data2;
|
||||
data = ENG_REG32(reg);
|
||||
data &= and_out;
|
||||
data |= or_in;
|
||||
data |= or_in2;
|
||||
ENG_RG32(reg) = data;
|
||||
ENG_REG32(reg) = data;
|
||||
}
|
||||
}
|
||||
else
|
||||
|
|
@ -1380,8 +1380,8 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
|
|||
LOG(8,("cmd 'WR 32bit reg $%08x = $%08x, then = $%08x' (always done)\n",
|
||||
reg, data, data2));
|
||||
/* always done */
|
||||
ENG_RG32(reg) = data;
|
||||
ENG_RG32(reg) = data2;
|
||||
ENG_REG32(reg) = data;
|
||||
ENG_REG32(reg) = data2;
|
||||
CFGW(ROMSHADOW, (CFGR(ROMSHADOW) & 0xfffffffe));
|
||||
break;
|
||||
case 0x69: /* identical to type1 */
|
||||
|
|
@ -1479,10 +1479,10 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
|
|||
reg, and_out, or_in));
|
||||
if (*exec)
|
||||
{
|
||||
data = ENG_RG32(reg);
|
||||
data = ENG_REG32(reg);
|
||||
data &= and_out;
|
||||
data |= or_in;
|
||||
ENG_RG32(reg) = data;
|
||||
ENG_REG32(reg) = data;
|
||||
}
|
||||
break;
|
||||
case 0x6f: /* new */
|
||||
|
|
@ -1522,7 +1522,7 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
|
|||
{
|
||||
reg2 = *((uint32*)(&(rom[(offset32 + (safe32 << 3))])));
|
||||
data2 = *((uint32*)(&(rom[(offset32 + (safe32 << 3) + 4)])));
|
||||
ENG_RG32(reg2) = data2;
|
||||
ENG_REG32(reg2) = data2;
|
||||
safe32++;
|
||||
}
|
||||
}
|
||||
|
|
@ -1598,7 +1598,7 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
|
|||
reg = *((uint32*)(&(rom[data])));
|
||||
and_out = *((uint32*)(&(rom[(data + 4)])));
|
||||
data2 = *((uint32*)(&(rom[(data + 8)])));
|
||||
data = ENG_RG32(reg);
|
||||
data = ENG_REG32(reg);
|
||||
data &= and_out;
|
||||
LOG(8,("cmd 'CHK bits AND-out $%08x reg $%08x for $%08x'\n",
|
||||
and_out, reg, data2));
|
||||
|
|
@ -1701,10 +1701,10 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
|
|||
uint8 m, n, p;
|
||||
eng_dac_sys_pll_find((data / 100.0), &calced_clk, &m, &n, &p, 0);
|
||||
/* programming the PLL needs to be done in steps! (confirmed NV28) */
|
||||
data2 = ENG_RG32(reg);
|
||||
ENG_RG32(reg) = ((data2 & 0xffff0000) | (n << 8) | m);
|
||||
data2 = ENG_RG32(reg);
|
||||
ENG_RG32(reg) = ((p << 16) | (n << 8) | m);
|
||||
data2 = ENG_REG32(reg);
|
||||
ENG_REG32(reg) = ((data2 & 0xffff0000) | (n << 8) | m);
|
||||
data2 = ENG_REG32(reg);
|
||||
ENG_REG32(reg) = ((p << 16) | (n << 8) | m);
|
||||
//fixme?
|
||||
/* program 2nd set N and M scalers if they exist (b31=1 enables them) */
|
||||
// if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36))
|
||||
|
|
@ -1729,7 +1729,7 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
|
|||
data = *((uint32*)(&(rom[*adress])));
|
||||
*adress += 4;
|
||||
LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x\n", reg, data));
|
||||
if (*exec) ENG_RG32(reg) = data;
|
||||
if (*exec) ENG_REG32(reg) = data;
|
||||
break;
|
||||
default:
|
||||
LOG(8,("unknown cmd, aborting!\n\n"));
|
||||
|
|
@ -1787,7 +1787,7 @@ static void setup_ram_config_nv10_up(uint8* rom)
|
|||
status_t stat = B_ERROR;
|
||||
|
||||
/* set 'refctrl is valid' */
|
||||
ENG_RG32(RG32_PFB_REFCTRL) = 0x80000000;
|
||||
ENG_REG32(RG32_PFB_REFCTRL) = 0x80000000;
|
||||
|
||||
/* check RAM for 256bits buswidth(?) */
|
||||
while ((cnt < 4) && (stat != B_OK))
|
||||
|
|
@ -1810,7 +1810,7 @@ static void setup_ram_config_nv10_up(uint8* rom)
|
|||
if (stat != B_OK)
|
||||
{
|
||||
LOG(8,("INFO: ---RAM test #1 done: access errors, modified setup.\n"));
|
||||
data = ENG_RG32(RG32_PFB_CONFIG_0);
|
||||
data = ENG_REG32(RG32_PFB_CONFIG_0);
|
||||
if (data & 0x00000010)
|
||||
{
|
||||
data &= 0xffffffcf;
|
||||
|
|
@ -1820,7 +1820,7 @@ static void setup_ram_config_nv10_up(uint8* rom)
|
|||
data &= 0xffffffcf;
|
||||
data |= 0x00000020;
|
||||
}
|
||||
ENG_RG32(RG32_PFB_CONFIG_0) = data;
|
||||
ENG_REG32(RG32_PFB_CONFIG_0) = data;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -1833,7 +1833,7 @@ static void setup_ram_config_nv10_up(uint8* rom)
|
|||
while ((cnt < 4) && (stat != B_OK))
|
||||
{
|
||||
/* read RAM size */
|
||||
data = ENG_RG32(RG32_NV10STRAPINFO);
|
||||
data = ENG_REG32(RG32_NV10STRAPINFO);
|
||||
/* subtract 1MB */
|
||||
data -= 0x00100000;
|
||||
/* write testpattern at generated RAM adress */
|
||||
|
|
@ -1854,7 +1854,7 @@ static void setup_ram_config_nv10_up(uint8* rom)
|
|||
if (stat != B_OK)
|
||||
{
|
||||
LOG(8,("INFO: ---RAM test #2 done: access errors, modified setup.\n"));
|
||||
ENG_RG32(RG32_PFB_CONFIG_0) &= 0xffffefff;
|
||||
ENG_REG32(RG32_PFB_CONFIG_0) &= 0xffffefff;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -1871,13 +1871,13 @@ static void setup_ram_config_nv28(uint8* rom)
|
|||
status_t stat = B_ERROR;
|
||||
|
||||
/* set 'refctrl is valid' */
|
||||
ENG_RG32(RG32_PFB_REFCTRL) = 0x80000000;
|
||||
ENG_REG32(RG32_PFB_REFCTRL) = 0x80000000;
|
||||
|
||||
/* check RAM */
|
||||
while ((cnt < 4) && (stat != B_OK))
|
||||
{
|
||||
/* set bit 11: 'pulse' something into a new setting? */
|
||||
ENG_RG32(RG32_PFB_CONFIG_0) |= 0x00000800;
|
||||
ENG_REG32(RG32_PFB_CONFIG_0) |= 0x00000800;
|
||||
/* write testpattern to RAM adress 127Mb */
|
||||
((uint32 *)si->framebuffer)[0x01fc0000] = 0x4e564441;
|
||||
/* reset first RAM adress */
|
||||
|
|
@ -1897,7 +1897,7 @@ static void setup_ram_config_nv28(uint8* rom)
|
|||
}
|
||||
|
||||
/* clear bit 11: set normal mode */
|
||||
ENG_RG32(RG32_PFB_CONFIG_0) &= ~0x00000800;
|
||||
ENG_REG32(RG32_PFB_CONFIG_0) &= ~0x00000800;
|
||||
|
||||
if (stat == B_OK)
|
||||
LOG(8,("INFO: ---RAM test done: access was OK within %d iteration(s).\n", cnt));
|
||||
|
|
@ -2334,7 +2334,7 @@ static void detect_panels()
|
|||
|
||||
/* dump some panel configuration registers... */
|
||||
LOG(2,("INFO: Dumping flatpanel registers:\n"));
|
||||
LOG(2,("DUALHEAD_CTRL: $%08x\n", ENG_RG32(RG32_DUALHEAD_CTRL)));
|
||||
LOG(2,("DUALHEAD_CTRL: $%08x\n", ENG_REG32(RG32_DUALHEAD_CTRL)));
|
||||
LOG(2,("DAC1: FP_HDISPEND: %d\n", DACR(FP_HDISPEND)));
|
||||
LOG(2,("DAC1: FP_HTOTAL: %d\n", DACR(FP_HTOTAL)));
|
||||
LOG(2,("DAC1: FP_HCRTC: %d\n", DACR(FP_HCRTC)));
|
||||
|
|
@ -2359,8 +2359,8 @@ static void detect_panels()
|
|||
LOG(2,("DAC1: FP_DEBUG2: $%08x\n", DACR(FP_DEBUG2)));
|
||||
LOG(2,("DAC1: FP_DEBUG3: $%08x\n", DACR(FP_DEBUG3)));
|
||||
|
||||
LOG(2,("DAC1: FUNCSEL: $%08x\n", ENG_RG32(RG32_FUNCSEL)));
|
||||
LOG(2,("DAC1: PANEL_PWR: $%08x\n", ENG_RG32(RG32_PANEL_PWR)));
|
||||
LOG(2,("DAC1: FUNCSEL: $%08x\n", ENG_REG32(RG32_FUNCSEL)));
|
||||
LOG(2,("DAC1: PANEL_PWR: $%08x\n", ENG_REG32(RG32_PANEL_PWR)));
|
||||
|
||||
if(si->ps.secondary_head)
|
||||
{
|
||||
|
|
@ -2388,8 +2388,8 @@ static void detect_panels()
|
|||
LOG(2,("DAC2: FP_DEBUG2: $%08x\n", DAC2R(FP_DEBUG2)));
|
||||
LOG(2,("DAC2: FP_DEBUG3: $%08x\n", DAC2R(FP_DEBUG3)));
|
||||
|
||||
LOG(2,("DAC2: FUNCSEL: $%08x\n", ENG_RG32(RG32_2FUNCSEL)));
|
||||
LOG(2,("DAC2: PANEL_PWR: $%08x\n", ENG_RG32(RG32_2PANEL_PWR)));
|
||||
LOG(2,("DAC2: FUNCSEL: $%08x\n", ENG_REG32(RG32_2FUNCSEL)));
|
||||
LOG(2,("DAC2: PANEL_PWR: $%08x\n", ENG_REG32(RG32_2PANEL_PWR)));
|
||||
}
|
||||
LOG(2,("INFO: End flatpanel registers dump.\n"));
|
||||
}
|
||||
|
|
@ -2850,7 +2850,7 @@ static void pinsnv30_arch_fake(void)
|
|||
|
||||
static void getRAMsize_arch_nv4(void)
|
||||
{
|
||||
uint32 strapinfo = ENG_RG32(RG32_NV4STRAPINFO);
|
||||
uint32 strapinfo = ENG_REG32(RG32_NV4STRAPINFO);
|
||||
|
||||
if (strapinfo & 0x00000100)
|
||||
{
|
||||
|
|
@ -2883,7 +2883,7 @@ static void getRAMsize_arch_nv4(void)
|
|||
|
||||
static void getstrap_arch_nv4(void)
|
||||
{
|
||||
uint32 strapinfo = ENG_RG32(RG32_NVSTRAPINFO2);
|
||||
uint32 strapinfo = ENG_REG32(RG32_NVSTRAPINFO2);
|
||||
|
||||
/* determine PLL reference crystal frequency */
|
||||
if (strapinfo & 0x00000040)
|
||||
|
|
@ -2898,7 +2898,7 @@ static void getstrap_arch_nv4(void)
|
|||
static void getRAMsize_arch_nv10_20_30_40(void)
|
||||
{
|
||||
uint32 dev_manID = CFGR(DEVID);
|
||||
uint32 strapinfo = ENG_RG32(RG32_NV10STRAPINFO);
|
||||
uint32 strapinfo = ENG_REG32(RG32_NV10STRAPINFO);
|
||||
|
||||
switch (dev_manID)
|
||||
{
|
||||
|
|
@ -2950,7 +2950,7 @@ static void getRAMsize_arch_nv10_20_30_40(void)
|
|||
static void getstrap_arch_nv10_20_30_40(void)
|
||||
{
|
||||
uint32 dev_manID = CFGR(DEVID);
|
||||
uint32 strapinfo = ENG_RG32(RG32_NVSTRAPINFO2);
|
||||
uint32 strapinfo = ENG_REG32(RG32_NVSTRAPINFO2);
|
||||
|
||||
/* determine PLL reference crystal frequency: three types are used... */
|
||||
if (strapinfo & 0x00000040)
|
||||
|
|
|
|||
Loading…
Reference in New Issue