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probably fixed NV31, NV36, and NV40 and higer core and ram PLL programming (new nv.settings tweaks).

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git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@16790 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen 2006-03-14 18:56:05 +00:00
parent dd822d46f6
commit ad78834e21
1 changed files with 5 additions and 2 deletions
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7
src/add-ons/accelerants/nvidia/engine/nv_info.c
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@ -2074,8 +2074,11 @@ void set_pll(uint32 reg, uint32 req_clk)
//fixme? //fixme?
/* program 2nd set N and M scalers if they exist (b31=1 enables them) */ /* program 2nd set N and M scalers if they exist (b31=1 enables them) */
/* program 2nd set N and M scalers if they exist (b31=1 enables them) */ if (si->ps.ext_pll)
if (si->ps.ext_pll) DACW(PIXPLLC2, 0x80000401); {
if (reg == NV32_COREPLL) NV_REG32(NV32_COREPLL2) = 0x80000401;
if (reg == NV32_MEMPLL) NV_REG32(NV32_MEMPLL2) = 0x80000401;
}
log_pll(reg, req_clk); log_pll(reg, req_clk);
} }