From ad78834e21549616ee9e83c510100e31a6837533 Mon Sep 17 00:00:00 2001 From: Rudolf Cornelissen Date: Tue, 14 Mar 2006 18:56:05 +0000 Subject: [PATCH] probably fixed NV31, NV36, and NV40 and higer core and ram PLL programming (new nv.settings tweaks). git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@16790 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- src/add-ons/accelerants/nvidia/engine/nv_info.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/add-ons/accelerants/nvidia/engine/nv_info.c b/src/add-ons/accelerants/nvidia/engine/nv_info.c index 34ef1009a5..8a9a763e0e 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_info.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_info.c @@ -2074,8 +2074,11 @@ void set_pll(uint32 reg, uint32 req_clk) //fixme? /* program 2nd set N and M scalers if they exist (b31=1 enables them) */ - /* program 2nd set N and M scalers if they exist (b31=1 enables them) */ - if (si->ps.ext_pll) DACW(PIXPLLC2, 0x80000401); + if (si->ps.ext_pll) + { + if (reg == NV32_COREPLL) NV_REG32(NV32_COREPLL2) = 0x80000401; + if (reg == NV32_MEMPLL) NV_REG32(NV32_MEMPLL2) = 0x80000401; + } log_pll(reg, req_clk); }