openBeOS_Nvidia_V0.05_src
git-svn-id: file:///srv/svn/repos/haiku/trunk/current@5505 a95241bf-73f2-0310-859d-f6bbb57e9c96
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shatty
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05b269c0ea
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@ -130,6 +130,7 @@ chip->PMC[0x00000140/4] = chip->EnableIRQ & 0x01;
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#define NV32_RASTER 0x00600808
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#define NV32_NV10CURADD32 0x0060080c
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#define NV32_CURCONF 0x00600810
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#define NV32_FUNCSEL 0x00600860
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/* secondary head */
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#define NV8_ATTR2INDW 0x006033c0
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@ -143,6 +144,7 @@ chip->PMC[0x00000140/4] = chip->EnableIRQ & 0x01;
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#define NV32_RASTER2 0x00602808//verify!!!
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#define NV32_NV10CUR2ADD32 0x0060280c//verify!!!
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#define NV32_2CURCONF 0x00602810//verify!!!
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#define NV32_2FUNCSEL 0x00602860
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/* Nvidia DAC direct registers (standard VGA palette RAM registers) */
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/* primary head */
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@ -255,9 +257,11 @@ chip->PMC[0x00000140/4] = chip->EnableIRQ & 0x01;
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#define NVBES_NV10_1DSTREF 0x0000894c
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#define NVBES_NV10_1DSTSIZE 0x00008954
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#define NVBES_NV10_1SRCPTCH 0x0000895c
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/* Nvidia MPEG2 hardware decoder (GeForce4MX only) */
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#define NVBES_DEC_GENCTRL 0x00001588
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/*
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chip->PMC[0x00008140/4] = 0;
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chip->PMC[0x00001588/4] = 0;
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*/
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//end new.
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@ -4,7 +4,7 @@
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Other authors:
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Mark Watson,
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Rudolf Cornelissen 4/2003
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Rudolf Cornelissen 4/2003-8/2003
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*/
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#define MODULE_BIT 0x20000000
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@ -24,7 +24,9 @@
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status_t SET_CURSOR_SHAPE(uint16 width, uint16 height, uint16 hot_x, uint16 hot_y, uint8 *andMask, uint8 *xorMask)
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{
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LOG(4,("SET_CURSOR_SHAPE: width %d, height %d\n", width, height));
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LOG(4,("SET_CURSOR_SHAPE: width %d, height %d, hot_x %d, hot_y %d\n",
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width, height, hot_x, hot_y));
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if ((width != 16) || (height != 16))
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{
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return B_ERROR;
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@ -142,9 +144,11 @@ void MOVE_CURSOR(uint16 x, uint16 y)
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//move_overlay(hds,vds);
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}
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/* put cursor in correct physical position */
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x -= hds + si->cursor.hot_x;
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y -= vds + si->cursor.hot_y;
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/* put cursor in correct physical position, so stay onscreen (rel. to CRTC) */
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if (x > (hds + si->cursor.hot_x)) x -= (hds + si->cursor.hot_x);
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else x = 0;
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if (y > (vds + si->cursor.hot_y)) y -= (vds + si->cursor.hot_y);
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else y = 0;
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/* account for switched CRTC's */
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if (si->switched_crtcs) x -= si->dm.timing.h_display;
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@ -429,9 +429,19 @@ status_t GET_OVERLAY_CONSTRAINTS
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}
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/* GeForce scaling restrictions */
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oc->h_scale.min = 0.125;
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switch (si->ps.card_arch)
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{
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case NV30A:
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/* GeForceFX series have a new BES engine... */
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oc->h_scale.min = 0.5;
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oc->v_scale.min = 0.5;
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break;
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default:
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oc->h_scale.min = 0.125;
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oc->v_scale.min = 0.125;
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break;
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}
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oc->h_scale.max = 16384/(float)(ob->width - si->overlay.myBufInfo[offset].slopspace);
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oc->v_scale.min = 0.125;
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oc->v_scale.max = 16384/(float)ob->height;
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return B_OK;
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@ -238,11 +238,25 @@ status_t nv_configure_bes
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hiscalv = ((((uint32)my_ov.width) << 16) / 16384);
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LOG(4,("Overlay: horizontal scaling factor too large, clamping at %f\n", (float)65536 / hiscalv));
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}
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if (hiscalv > (8 << 16))
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switch (si->ps.card_arch)
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{
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/* (non-inverse) factor too small, set factor to min. valid value */
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hiscalv = (8 << 16);
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LOG(4,("Overlay: horizontal scaling factor too small, clamping at %f\n", (float)65536 / hiscalv));
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case NV30A:
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/* GeForceFX series have a downscaling limit of 0.5 */
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if (hiscalv > (2 << 16))
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{
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/* (non-inverse) factor too small, set factor to min. valid value */
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hiscalv = (2 << 16);
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LOG(4,("Overlay: horizontal scaling factor too small, clamping at %f\n", (float)65536 / hiscalv));
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}
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break;
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default:
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if (hiscalv > (8 << 16))
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{
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/* (non-inverse) factor too small, set factor to min. valid value */
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hiscalv = (8 << 16);
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LOG(4,("Overlay: horizontal scaling factor too small, clamping at %f\n", (float)65536 / hiscalv));
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}
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break;
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}
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/* AND below is required by hardware */
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hiscalv &= 0x001ffffc;
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@ -338,11 +352,25 @@ status_t nv_configure_bes
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viscalv = ((((uint32)my_ov.height) << 16) / 16384);
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LOG(4,("Overlay: vertical scaling factor too large, clamping at %f\n", (float)65536 / viscalv));
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}
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if (viscalv > (8 << 16))
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switch (si->ps.card_arch)
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{
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/* (non-inverse) factor too small, set factor to min. valid value */
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viscalv = (8 << 16);
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LOG(4,("Overlay: vertical scaling factor too small, clamping at %f\n", (float)65536 / viscalv));
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case NV30A:
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/* GeForceFX series have a downscaling limit of 0.5 */
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if (viscalv > (2 << 16))
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{
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/* (non-inverse) factor too small, set factor to min. valid value */
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viscalv = (2 << 16);
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LOG(4,("Overlay: vertical scaling factor too small, clamping at %f\n", (float)65536 / viscalv));
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}
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break;
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default:
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if (viscalv > (8 << 16))
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{
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/* (non-inverse) factor too small, set factor to min. valid value */
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viscalv = (8 << 16);
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LOG(4,("Overlay: vertical scaling factor too small, clamping at %f\n", (float)65536 / viscalv));
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}
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break;
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}
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/* AND below is required by hardware */
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viscalv &= 0x001ffffc;
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@ -430,6 +458,8 @@ status_t nv_configure_bes
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*** actually program the registers ***
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**************************************/
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/* shut off GeForce4MX MPEG2 decoder */
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BESW(DEC_GENCTRL, 0x00000000);
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/* We only use buffer buffer 0: select it. (0x01 = buffer 0, 0x10 = buffer 1) */
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BESW(NV10_BUFSEL, 0x00000001);
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/* setup buffer origin: GeForce uses subpixel precise clipping on left and top! (12.4 values) */
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@ -81,7 +81,7 @@ status_t nv_general_powerup()
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{
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status_t status;
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LOG(1,("POWERUP: nVidia (open)BeOS Accelerant 0.04 running.\n"));
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LOG(1,("POWERUP: nVidia (open)BeOS Accelerant 0.05 running.\n"));
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/* preset no laptop */
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si->ps.laptop = false;
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@ -739,7 +739,7 @@ status_t nv_general_bios_to_powergraphics()
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nv_crtc_cursor_hide();
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/* power-up all nvidia hardware function blocks */
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/* bit 28: PVIDEO,
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/* bit 28: OVERLAY ENGINE (BES),
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* bit 25: CRTC2, (> NV04A)
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* bit 24: CRTC1,
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* bit 20: framebuffer,
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@ -750,6 +750,11 @@ status_t nv_general_bios_to_powergraphics()
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* bit 0: TVOUT. (> NV04A) */
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NV_REG32(NV32_PWRUPCTRL) = 0x13111111;
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/* switch overlay engine to head 1 */
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//fixme: add other function blocks...
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NV_REG32(NV32_FUNCSEL) |= 0x00001000;
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NV_REG32(NV32_2FUNCSEL) &= ~0x00001000;
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/* set card to 'enhanced' mode: (only VGA standard registers used for NeoMagic cards) */
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/* (keep) card enabled, set plain normal memory usage, no old VGA 'tricks' ... */
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// CRTCW(MODECTL, 0xc3);
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