887d4abb1d
git-svn-id: file:///srv/svn/repos/haiku/trunk/current@5505 a95241bf-73f2-0310-859d-f6bbb57e9c96
435 lines
15 KiB
C
435 lines
15 KiB
C
/* NV registers definitions and macros for access to */
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//new:
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/* PCI_config_space */
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#define NVCFG_DEVID 0x00
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#define NVCFG_DEVCTRL 0x04
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#define NVCFG_CLASS 0x08
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#define NVCFG_HEADER 0x0c
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#define NVCFG_BASE1REGS 0x10
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#define NVCFG_BASE2FB 0x14
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#define NVCFG_BASE3 0x18
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#define NVCFG_BASE4 0x1c //unknown if used
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#define NVCFG_BASE5 0x20 //unknown if used
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#define NVCFG_BASE6 0x24 //unknown if used
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#define NVCFG_BASE7 0x28 //unknown if used
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#define NVCFG_SUBSYSID1 0x2c
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#define NVCFG_ROMBASE 0x30
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#define NVCFG_CFG_0 0x34
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#define NVCFG_CFG_1 0x38 //unknown if used
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#define NVCFG_INTERRUPT 0x3c
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#define NVCFG_SUBSYSID2 0x40
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#define NVCFG_AGPREF 0x44
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#define NVCFG_AGPSTAT 0x48
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#define NVCFG_AGPCMD 0x4c
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#define NVCFG_ROMSHADOW 0x50
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#define NVCFG_VGA 0x54
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#define NVCFG_SCHRATCH 0x58
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#define NVCFG_CFG_10 0x5c
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#define NVCFG_CFG_11 0x60
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#define NVCFG_CFG_12 0x64
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#define NVCFG_CFG_13 0x68 //unknown if used
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#define NVCFG_CFG_14 0x6c //unknown if used
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#define NVCFG_CFG_15 0x70 //unknown if used
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#define NVCFG_CFG_16 0x74 //unknown if used
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#define NVCFG_CFG_17 0x78 //unknown if used
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#define NVCFG_GF2IGPU 0x7c
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#define NVCFG_CFG_19 0x80 //unknown if used
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#define NVCFG_GF4MXIGPU 0x84
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#define NVCFG_CFG_21 0x88 //unknown if used
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#define NVCFG_CFG_22 0x8c //unknown if used
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#define NVCFG_CFG_23 0x90 //unknown if used
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#define NVCFG_CFG_24 0x94 //unknown if used
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#define NVCFG_CFG_25 0x98 //unknown if used
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#define NVCFG_CFG_26 0x9c //unknown if used
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#define NVCFG_CFG_27 0xa0 //unknown if used
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#define NVCFG_CFG_28 0xa4 //unknown if used
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#define NVCFG_CFG_29 0xa8 //unknown if used
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#define NVCFG_CFG_30 0xac //unknown if used
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#define NVCFG_CFG_31 0xb0 //unknown if used
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#define NVCFG_CFG_32 0xb4 //unknown if used
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#define NVCFG_CFG_33 0xb8 //unknown if used
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#define NVCFG_CFG_34 0xbc //unknown if used
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#define NVCFG_CFG_35 0xc0 //unknown if used
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#define NVCFG_CFG_36 0xc4 //unknown if used
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#define NVCFG_CFG_37 0xc8 //unknown if used
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#define NVCFG_CFG_38 0xcc //unknown if used
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#define NVCFG_CFG_39 0xd0 //unknown if used
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#define NVCFG_CFG_40 0xd4 //unknown if used
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#define NVCFG_CFG_41 0xd8 //unknown if used
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#define NVCFG_CFG_42 0xdc //unknown if used
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#define NVCFG_CFG_43 0xe0 //unknown if used
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#define NVCFG_CFG_44 0xe4 //unknown if used
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#define NVCFG_CFG_45 0xe8 //unknown if used
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#define NVCFG_CFG_46 0xec //unknown if used
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#define NVCFG_CFG_47 0xf0 //unknown if used
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#define NVCFG_CFG_48 0xf4 //unknown if used
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#define NVCFG_CFG_49 0xf8 //unknown if used
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#define NVCFG_CFG_50 0xfc //unknown if used
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/* if(pNv->SecondCRTC) {
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pNv->riva.PCIO = pNv->riva.PCIO0 + 0x2000;
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pNv->riva.PCRTC = pNv->riva.PCRTC0 + 0x800;
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pNv->riva.PRAMDAC = pNv->riva.PRAMDAC0 + 0x800;
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pNv->riva.PDIO = pNv->riva.PDIO0 + 0x2000;
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} else {
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pNv->riva.PCIO = pNv->riva.PCIO0;
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pNv->riva.PCRTC = pNv->riva.PCRTC0;
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pNv->riva.PRAMDAC = pNv->riva.PRAMDAC0;
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pNv->riva.PDIO = pNv->riva.PDIO0;
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}
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*/
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/*
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* These registers are read/write as 8 bit values. Probably have to map
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* sparse on alpha.
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*/
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/* pNv->riva.PCIO0 = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags,
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pNv->PciTag, regBase+0x00601000,
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0x00003000);
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pNv->riva.PDIO0 = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags,
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pNv->PciTag, regBase+0x00681000,
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0x00003000);
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pNv->riva.PVIO = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags,
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pNv->PciTag, regBase+0x000C0000,
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0x00001000);
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pNv->riva.PRAMDAC0 = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag,
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regBase+0x00680000, 0x00003000);
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pNv->riva.PCRTC0 = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag,
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regBase+0x00600000, 0x00003000);
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Set interrupt enable.
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chip->PMC[0x00000140/4] = chip->EnableIRQ & 0x01;
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*/
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/* Nvidia PCI direct registers */
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#define NV32_PWRUPCTRL 0x00000200
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#define NV8_MISCW 0x000c03c2
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#define NV8_MISCR 0x000c03cc
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#define NV8_SEQIND 0x000c03c4
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#define NV16_SEQIND 0x000c03c4
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#define NV8_SEQDAT 0x000c03c5
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#define NV8_GRPHIND 0x000c03ce
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#define NV16_GRPHIND 0x000c03ce
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#define NV8_GRPHDAT 0x000c03cf
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/* bootstrap info registers */
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#define NV32_NV4STRAPINFO 0x00100000
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#define NV32_NV10STRAPINFO 0x0010020c
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#define NV32_NVSTRAPINFO2 0x00101000
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/* primary head */
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#define NV8_ATTRINDW 0x006013c0
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#define NV8_ATTRDATW 0x006013c0
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#define NV8_ATTRDATR 0x006013c1
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#define NV8_CRTCIND 0x006013d4
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#define NV16_CRTCIND 0x006013d4
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#define NV8_CRTCDAT 0x006013d5
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#define NV8_INSTAT1 0x006013da
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#define NV32_NV10FBSTADD32 0x00600800
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#define NV32_CONFIG 0x00600804//not yet used (coldstart)...
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#define NV32_RASTER 0x00600808
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#define NV32_NV10CURADD32 0x0060080c
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#define NV32_CURCONF 0x00600810
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#define NV32_FUNCSEL 0x00600860
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/* secondary head */
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#define NV8_ATTR2INDW 0x006033c0
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#define NV8_ATTR2DATW 0x006033c0
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#define NV8_ATTR2DATR 0x006033c1
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#define NV8_CRTC2IND 0x006033d4
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#define NV16_CRTC2IND 0x006033d4
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#define NV8_CRTC2DAT 0x006033d5
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#define NV8_2INSTAT1 0x006033da//verify!!!
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#define NV32_NV10FB2STADD32 0x00602800//verify!!!
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#define NV32_RASTER2 0x00602808//verify!!!
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#define NV32_NV10CUR2ADD32 0x0060280c//verify!!!
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#define NV32_2CURCONF 0x00602810//verify!!!
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#define NV32_2FUNCSEL 0x00602860
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/* Nvidia DAC direct registers (standard VGA palette RAM registers) */
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/* primary head */
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#define NV8_PALMASK 0x006813c6
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#define NV8_PALINDR 0x006813c7
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#define NV8_PALINDW 0x006813c8
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#define NV8_PALDATA 0x006813c9
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/* secondary head */
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#define NV8_PAL2MASK 0x006833c6//verify!!!
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#define NV8_PAL2INDR 0x006833c7//verify!!!
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#define NV8_PAL2INDW 0x006833c8//verify!!!
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#define NV8_PAL2DATA 0x006833c9//verify!!!
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/* Nvidia PCI direct DAC registers (32bit) */
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/* primary head */
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#define NVDAC_CURPOS 0x00680300
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#define NVDAC_PIXPLLC 0x00680508
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#define NVDAC_PLLSEL 0x0068050c
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#define NVDAC_GENCTRL 0x00680600
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/* secondary head */
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#define NVDAC2_CURPOS 0x00680b00
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#define NVDAC2_PIXPLLC 0x00680d20//verify!!!
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#define NVDAC2_PLLSEL 0x00680d0c//verify!!!
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#define NVDAC2_GENCTRL 0x00680e00//verify!!!
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/* Nvidia CRTC indexed registers */
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/* VGA standard registers: */
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#define NVCRTCX_HTOTAL 0x00
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#define NVCRTCX_HDISPE 0x01
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#define NVCRTCX_HBLANKS 0x02
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#define NVCRTCX_HBLANKE 0x03
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#define NVCRTCX_HSYNCS 0x04
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#define NVCRTCX_HSYNCE 0x05
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#define NVCRTCX_VTOTAL 0x06
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#define NVCRTCX_OVERFLOW 0x07
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#define NVCRTCX_PRROWSCN 0x08
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#define NVCRTCX_MAXSCLIN 0x09
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#define NVCRTCX_VGACURCTRL 0x0a
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#define NVCRTCX_FBSTADDH 0x0c //confirmed
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#define NVCRTCX_FBSTADDL 0x0d //confirmed
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#define NVCRTCX_VSYNCS 0x10
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#define NVCRTCX_VSYNCE 0x11
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#define NVCRTCX_VDISPE 0x12
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#define NVCRTCX_PITCHL 0x13 //confirmed
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#define NVCRTCX_VBLANKS 0x15
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#define NVCRTCX_VBLANKE 0x16
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#define NVCRTCX_MODECTL 0x17
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#define NVCRTCX_LINECOMP 0x18
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/* Nvidia specific registers: */
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#define NVCRTCX_REPAINT0 0x19
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#define NVCRTCX_REPAINT1 0x1a
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#define NVCRTCX_LOCK 0x1f
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#define NVCRTCX_LSR 0x25
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#define NVCRTCX_PIXEL 0x28
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#define NVCRTCX_HEB 0x2d
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#define NVCRTCX_CURCTL2 0x2f
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#define NVCRTCX_CURCTL1 0x30
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#define NVCRTCX_CURCTL0 0x31
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/* Nvidia ATTRIBUTE indexed registers */
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/* VGA standard registers: */
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#define NVATBX_MODECTL 0x10
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#define NVATBX_OSCANCOLOR 0x11
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#define NVATBX_COLPLANE_EN 0x12
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#define NVATBX_HORPIXPAN 0x13 //confirmed
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#define NVATBX_COLSEL 0x14
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/* Nvidia SEQUENCER indexed registers */
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/* VGA standard registers: */
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#define NVSEQX_RESET 0x00
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#define NVSEQX_CLKMODE 0x01
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#define NVSEQX_MEMMODE 0x04
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/* Nvidia GRAPHICS indexed registers */
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/* VGA standard registers: */
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#define NVGRPHX_ENSETRESET 0x01
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#define NVGRPHX_DATAROTATE 0x03
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#define NVGRPHX_READMAPSEL 0x04
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#define NVGRPHX_MODE 0x05
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#define NVGRPHX_MISC 0x06
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#define NVGRPHX_BITMASK 0x08
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/* Nvidia BES (Back End Scaler) registers (>= NV10) */
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#define NVBES_NV10_BUFSEL 0x00008700
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#define NVBES_NV10_GENCTRL 0x00008704
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#define NVBES_NV10_COLKEY 0x00008b00
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/* buffer 0 */
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#define NVBES_NV10_0BUFADR 0x00008900
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#define NVBES_NV10_0MEMMASK 0x00008908
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#define NVBES_NV10_0BRICON 0x00008910
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#define NVBES_NV10_0SAT 0x00008918
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#define NVBES_NV10_0WHAT 0x00008920
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#define NVBES_NV10_0SRCSIZE 0x00008928
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#define NVBES_NV10_0SRCREF 0x00008930
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#define NVBES_NV10_0ISCALH 0x00008938
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#define NVBES_NV10_0ISCALV 0x00008940
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#define NVBES_NV10_0DSTREF 0x00008948
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#define NVBES_NV10_0DSTSIZE 0x00008950
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#define NVBES_NV10_0SRCPTCH 0x00008958
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/* buffer 1 */
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#define NVBES_NV10_1BUFADR 0x00008904
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#define NVBES_NV10_1MEMMASK 0x0000890c
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#define NVBES_NV10_1BRICON 0x00008914
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#define NVBES_NV10_1SAT 0x0000891c
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#define NVBES_NV10_1WHAT 0x00008924
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#define NVBES_NV10_1SRCSIZE 0x0000892c
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#define NVBES_NV10_1SRCREF 0x00008934
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#define NVBES_NV10_1ISCALH 0x0000893c
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#define NVBES_NV10_1ISCALV 0x00008944
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#define NVBES_NV10_1DSTREF 0x0000894c
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#define NVBES_NV10_1DSTSIZE 0x00008954
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#define NVBES_NV10_1SRCPTCH 0x0000895c
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/* Nvidia MPEG2 hardware decoder (GeForce4MX only) */
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#define NVBES_DEC_GENCTRL 0x00001588
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/*
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chip->PMC[0x00008140/4] = 0;
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*/
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//end new.
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/* NV 2nd CRTC registers (>= G400) */
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#define NVCR2_CTL 0x3C10
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#define NVCR2_HPARAM 0x3C14
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#define NVCR2_HSYNC 0x3C18
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#define NVCR2_VPARAM 0x3C1C
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#define NVCR2_VSYNC 0x3C20
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#define NVCR2_PRELOAD 0x3C24
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#define NVCR2_STARTADD0 0x3C28
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#define NVCR2_STARTADD1 0x3C2C
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#define NVCR2_OFFSET 0x3C40
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#define NVCR2_MISC 0x3C44
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#define NVCR2_VCOUNT 0x3C48
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#define NVCR2_DATACTL 0x3C4C
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/* NV ACCeleration registers */
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#define NVACC_DWGCTL 0x1C00
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#define NVACC_MACCESS 0x1C04
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#define NVACC_MCTLWTST 0x1C08
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#define NVACC_ZORG 0x1C0C
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#define NVACC_PLNWT 0x1C1C
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#define NVACC_BCOL 0x1C20
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#define NVACC_FCOL 0x1C24
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#define NVACC_XYSTRT 0x1C40
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#define NVACC_XYEND 0x1C44
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#define NVACC_SGN 0x1C58
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#define NVACC_LEN 0x1C5C
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#define NVACC_AR0 0x1C60
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#define NVACC_AR3 0x1C6C
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#define NVACC_AR5 0x1C74
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#define NVACC_CXBNDRY 0x1C80
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#define NVACC_FXBNDRY 0x1C84
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#define NVACC_YDSTLEN 0x1C88
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#define NVACC_PITCH 0x1C8C
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#define NVACC_YDST 0x1C90
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#define NVACC_YDSTORG 0x1C94
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#define NVACC_YTOP 0x1C98
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#define NVACC_YBOT 0x1C9C
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#define NVACC_CXLEFT 0x1CA0
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#define NVACC_CXRIGHT 0x1CA4
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#define NVACC_FXLEFT 0x1CA8
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#define NVACC_FXRIGHT 0x1CAC
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#define NVACC_STATUS 0x1E14
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#define NVACC_ICLEAR 0x1E18 /* required for interrupt stuff */
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#define NVACC_IEN 0x1E1C /* required for interrupt stuff */
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#define NVACC_RST 0x1E40
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#define NVACC_MEMRDBK 0x1E44
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#define NVACC_OPMODE 0x1E54
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#define NVACC_PRIMADDRESS 0x1E58
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#define NVACC_PRIMEND 0x1E5C
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#define NVACC_TEXORG 0x2C24 // >= G100
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#define NVACC_DWGSYNC 0x2C4C // >= G200
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#define NVACC_TEXORG1 0x2CA4 // >= G200
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#define NVACC_TEXORG2 0x2CA8 // >= G200
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#define NVACC_TEXORG3 0x2CAC // >= G200
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#define NVACC_TEXORG4 0x2CB0 // >= G200
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#define NVACC_SRCORG 0x2CB4 // >= G200
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#define NVACC_DSTORG 0x2CB8 // >= G200
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/*MAVEN registers (<= G400) */
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#define NVMAV_PGM 0x3E
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#define NVMAV_PIXPLLM 0x80
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#define NVMAV_PIXPLLN 0x81
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#define NVMAV_PIXPLLP 0x82
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#define NVMAV_GAMMA1 0x83
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#define NVMAV_GAMMA2 0x84
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#define NVMAV_GAMMA3 0x85
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#define NVMAV_GAMMA4 0x86
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#define NVMAV_GAMMA5 0x87
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#define NVMAV_GAMMA6 0x88
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#define NVMAV_GAMMA7 0x89
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#define NVMAV_GAMMA8 0x8A
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#define NVMAV_GAMMA9 0x8B
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#define NVMAV_MONSET 0x8C
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#define NVMAV_TEST 0x8D
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#define NVMAV_WREG_0X8E_L 0x8E
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#define NVMAV_WREG_0X8E_H 0x8F
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#define NVMAV_HSCALETV 0x90
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#define NVMAV_TSCALETVL 0x91
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#define NVMAV_TSCALETVH 0x92
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#define NVMAV_FFILTER 0x93
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#define NVMAV_MONEN 0x94
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#define NVMAV_RESYNC 0x95
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#define NVMAV_LASTLINEL 0x96
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#define NVMAV_LASTLINEH 0x97
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#define NVMAV_WREG_0X98_L 0x98
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#define NVMAV_WREG_0X98_H 0x99
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#define NVMAV_HSYNCLENL 0x9A
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#define NVMAV_HSYNCLENH 0x9B
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#define NVMAV_HSYNCSTRL 0x9C
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#define NVMAV_HSYNCSTRH 0x9D
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#define NVMAV_HDISPLAYL 0x9E
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#define NVMAV_HDISPLAYH 0x9F
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#define NVMAV_HTOTALL 0xA0
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#define NVMAV_HTOTALH 0xA1
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#define NVMAV_VSYNCLENL 0xA2
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#define NVMAV_VSYNCLENH 0xA3
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#define NVMAV_VSYNCSTRL 0xA4
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#define NVMAV_VSYNCSTRH 0xA5
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#define NVMAV_VDISPLAYL 0xA6
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#define NVMAV_VDISPLAYH 0xA7
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#define NVMAV_VTOTALL 0xA8
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#define NVMAV_VTOTALH 0xA9
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#define NVMAV_HVIDRSTL 0xAA
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#define NVMAV_HVIDRSTH 0xAB
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#define NVMAV_VVIDRSTL 0xAC
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#define NVMAV_VVIDRSTH 0xAD
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#define NVMAV_VSOMETHINGL 0xAE
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#define NVMAV_VSOMETHINGH 0xAF
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#define NVMAV_OUTMODE 0xB0
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#define NVMAV_LOCK 0xB3
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#define NVMAV_LUMA 0xB9
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#define NVMAV_VDISPLAYTV 0xBE
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#define NVMAV_STABLE 0xBF
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#define NVMAV_HDISPLAYTV 0xC2
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#define NVMAV_BREG_0XC6 0xC6
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//new:
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/* Macros for convenient accesses to the NV chips */
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#define NV_REG8(r_) ((vuint8 *)regs)[(r_)]
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#define NV_REG16(r_) ((vuint16 *)regs)[(r_) >> 1]
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#define NV_REG32(r_) ((vuint32 *)regs)[(r_) >> 2]
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/* read and write to PCI config space */
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#define CFGR(A) (nv_pci_access.offset=NVCFG_##A, ioctl(fd,NV_GET_PCI, &nv_pci_access,sizeof(nv_pci_access)), nv_pci_access.value)
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#define CFGW(A,B) (nv_pci_access.offset=NVCFG_##A, nv_pci_access.value = B, ioctl(fd,NV_SET_PCI,&nv_pci_access,sizeof(nv_pci_access)))
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/* read and write from the dac registers */
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#define DACR(A) (NV_REG32(NVDAC_##A))
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#define DACW(A,B) (NV_REG32(NVDAC_##A)=B)
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#define DAC2R(A) (NV_REG32(NVDAC2_##A))
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#define DAC2W(A,B) (NV_REG32(NVDAC2_##A)=B)
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/* read and write from the backend scaler registers */
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#define BESR(A) (NV_REG32(NVBES_##A))
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#define BESW(A,B) (NV_REG32(NVBES_##A)=B)
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/* read and write from CRTC indexed registers */
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#define CRTCW(A,B)(NV_REG16(NV16_CRTCIND) = ((NVCRTCX_##A) | ((B) << 8)))
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#define CRTCR(A) (NV_REG8(NV8_CRTCIND) = (NVCRTCX_##A), NV_REG8(NV8_CRTCDAT))
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/* read and write from ATTRIBUTE indexed registers */
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#define ATBW(A,B)(NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTRINDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTRDATW) = (B))
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#define ATBR(A) (NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTRINDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTRDATR))
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/* read and write from SEQUENCER indexed registers */
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#define SEQW(A,B)(NV_REG16(NV16_SEQIND) = ((NVSEQX_##A) | ((B) << 8)))
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#define SEQR(A) (NV_REG8(NV8_SEQIND) = (NVSEQX_##A), NV_REG8(NV8_SEQDAT))
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/* read and write from PCI GRAPHICS indexed registers */
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#define GRPHW(A,B)(NV_REG16(NV16_GRPHIND) = ((NVGRPHX_##A) | ((B) << 8)))
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#define GRPHR(A) (NV_REG8(NV8_GRPHIND) = (NVGRPHX_##A), NV_REG8(NV8_GRPHDAT))
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//end new.
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/* read and write from maven (<= G400) */
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#define MAVR(A) (i2c_maven_read (NVMAV_##A ))
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#define MAVW(A,B) (i2c_maven_write(NVMAV_##A ,B))
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#define MAVRW(A) (i2c_maven_read (NVMAV_##A )|(i2c_maven_read(NVMAV_##A +1)<<8))
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#define MAVWW(A,B) (i2c_maven_write(NVMAV_##A ,B &0xFF),i2c_maven_write(NVMAV_##A +1,B >>8))
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/* read and write from the powergraphics registers */
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#define ACCR(A) (NV_REG32(NVACC_##A))
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#define ACCW(A,B) (NV_REG32(NVACC_##A)=B)
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#define ACCGO(A,B) (NV_REG32(NVACC_##A + 0x0100)=B)
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/* read and write from second CRTC */
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#define CR2R(A) (NV_REG32(NVCR2_##A))
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#define CR2W(A,B) (NV_REG32(NVCR2_##A)=B)
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