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* memory_base isn't what I thought it was and is 0x0

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* look at PCI bar 0 (Frame buffer base) for AtomBIOS
* potential solution to #8040 ?


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42903 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Alexander von Gluck IV 2011-10-24 17:03:48 +00:00
parent bc096b828e
commit 6f2ec43df7
1 changed files with 5 additions and 2 deletions
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7
src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp
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@ -63,9 +63,12 @@ radeon_hd_getbios(radeon_info &info)
uint32 romConfig = 0;
if (info.isIGP == true) {
romBase = info.pci->u.h1.memory_base;
// IGP chipsets don't have a PCI rom BAR.
// On post, the bios puts a copy of the IGP
// AtomBIOS at the start of the video ram
romBase = info.pci->u.h0.base_registers[RHD_FB_BAR];
romSize = 256 * 1024;
// a complete guess
// romSize an educated guess
} else {
// Enable ROM decoding for PCI bar rom
romConfig = get_pci_config(info.pci, PCI_rom_base, 4);