From 6f2ec43df7c09a69f587f43e3cbc0fc20eac9f03 Mon Sep 17 00:00:00 2001 From: Alexander von Gluck IV Date: Mon, 24 Oct 2011 17:03:48 +0000 Subject: [PATCH] * memory_base isn't what I thought it was and is 0x0 * look at PCI bar 0 (Frame buffer base) for AtomBIOS * potential solution to #8040 ? git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42903 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- .../kernel/drivers/graphics/radeon_hd/radeon_hd.cpp | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp b/src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp index 1cbf24d2b7..f1aac4a644 100644 --- a/src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp +++ b/src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp @@ -63,9 +63,12 @@ radeon_hd_getbios(radeon_info &info) uint32 romConfig = 0; if (info.isIGP == true) { - romBase = info.pci->u.h1.memory_base; + // IGP chipsets don't have a PCI rom BAR. + // On post, the bios puts a copy of the IGP + // AtomBIOS at the start of the video ram + romBase = info.pci->u.h0.base_registers[RHD_FB_BAR]; romSize = 256 * 1024; - // a complete guess + // romSize an educated guess } else { // Enable ROM decoding for PCI bar rom romConfig = get_pci_config(info.pci, PCI_rom_base, 4);