radeon_hd: enable non-dp code to execute dpcd queries
* Check DPCD to properly choose TRAVIS DP panel mode
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5f44fcce9f
@ -160,14 +160,14 @@ dp_aux_read(uint32 hwPin, uint16 address,
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}
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static void
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void
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dpcd_reg_write(uint32 hwPin, uint16 address, uint8 value)
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{
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dp_aux_write(hwPin, address, &value, 1, 0);
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}
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static uint8
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uint8
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dpcd_reg_read(uint32 hwPin, uint16 address)
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{
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uint8 value = 0;
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@ -22,6 +22,9 @@
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#define DP_TPS3_SUPPORTED (1 << 6) // Stored within MAX_LANE_COUNT
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uint8 dpcd_reg_read(uint32 hwPin, uint16 address);
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void dpcd_reg_write(uint32 hwPin, uint16 address, uint8 value);
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int dp_aux_write(uint32 hwPin, uint16 address, uint8* send,
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uint8 sendBytes, uint8 delay);
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int dp_aux_read(uint32 hwPin, uint16 address, uint8* recv,
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@ -589,9 +589,17 @@ encoder_dig_setup(uint32 connectorIndex, uint32 pixelClock, int command)
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panelMode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
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else if (connector->encoderExternal.objectID
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== ENCODER_OBJECT_ID_TRAVIS) {
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TRACE("%s: TODO: Travis: read DP confg data, DP1 vs DP2 mode\n",
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__func__);
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panelMode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
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dp_info* dp = &gConnector[connectorIndex]->dpInfo;
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uint8 id[6];
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int bit;
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for (bit = 0; bit < 6; bit++)
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id[bit] = dpcd_reg_read(dp->auxPin, 0x503 + bit);
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if (id[0] == 0x73 && id[1] == 0x69 && id[2] == 0x76
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&& id[3] == 0x61 && id[4] == 0x72 && id[5] == 0x54) {
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panelMode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
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} else {
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panelMode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
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}
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} else {
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panelMode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
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}
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@ -1345,7 +1353,7 @@ transmitter_dig_setup(uint32 connectorIndex, uint32 pixelClock,
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// DP PHY to be clocked from external src if possible
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if (isDP && pll->dpExternalClock) {
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// use external clock source
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args.v3.acConfig.ucRefClkSource = 2;
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args.v3.acConfig.ucRefClkSource = ATOM_DCPLL;
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} else
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args.v3.acConfig.ucRefClkSource = pll->id;
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