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radeon_hd: enable non-dp code to execute dpcd queries

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* Check DPCD to properly choose TRAVIS DP panel mode
This commit is contained in:
Alexander von Gluck IV 2012-08-07 07:24:42 -05:00
parent 472744339b
commit 5f44fcce9f
3 changed files with 17 additions and 6 deletions
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4
src/add-ons/accelerants/radeon_hd/displayport.cpp
View File

@ -160,14 +160,14 @@ dp_aux_read(uint32 hwPin, uint16 address,
} }
static void void
dpcd_reg_write(uint32 hwPin, uint16 address, uint8 value) dpcd_reg_write(uint32 hwPin, uint16 address, uint8 value)
{ {
dp_aux_write(hwPin, address, &value, 1, 0); dp_aux_write(hwPin, address, &value, 1, 0);
} }
static uint8 uint8
dpcd_reg_read(uint32 hwPin, uint16 address) dpcd_reg_read(uint32 hwPin, uint16 address)
{ {
uint8 value = 0; uint8 value = 0;

3
src/add-ons/accelerants/radeon_hd/displayport.h
View File

@ -22,6 +22,9 @@
#define DP_TPS3_SUPPORTED (1 << 6) // Stored within MAX_LANE_COUNT #define DP_TPS3_SUPPORTED (1 << 6) // Stored within MAX_LANE_COUNT
uint8 dpcd_reg_read(uint32 hwPin, uint16 address);
void dpcd_reg_write(uint32 hwPin, uint16 address, uint8 value);
int dp_aux_write(uint32 hwPin, uint16 address, uint8* send, int dp_aux_write(uint32 hwPin, uint16 address, uint8* send,
uint8 sendBytes, uint8 delay); uint8 sendBytes, uint8 delay);
int dp_aux_read(uint32 hwPin, uint16 address, uint8* recv, int dp_aux_read(uint32 hwPin, uint16 address, uint8* recv,

16
src/add-ons/accelerants/radeon_hd/encoder.cpp
View File

@ -589,9 +589,17 @@ encoder_dig_setup(uint32 connectorIndex, uint32 pixelClock, int command)
panelMode = DP_PANEL_MODE_INTERNAL_DP1_MODE; panelMode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
else if (connector->encoderExternal.objectID else if (connector->encoderExternal.objectID
== ENCODER_OBJECT_ID_TRAVIS) { == ENCODER_OBJECT_ID_TRAVIS) {
TRACE("%s: TODO: Travis: read DP confg data, DP1 vs DP2 mode\n", dp_info* dp = &gConnector[connectorIndex]->dpInfo;
__func__); uint8 id[6];
panelMode = DP_PANEL_MODE_INTERNAL_DP1_MODE; int bit;
for (bit = 0; bit < 6; bit++)
id[bit] = dpcd_reg_read(dp->auxPin, 0x503 + bit);
if (id[0] == 0x73 && id[1] == 0x69 && id[2] == 0x76
&& id[3] == 0x61 && id[4] == 0x72 && id[5] == 0x54) {
panelMode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
} else {
panelMode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
}
} else { } else {
panelMode = DP_PANEL_MODE_INTERNAL_DP2_MODE; panelMode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
} }
@ -1345,7 +1353,7 @@ transmitter_dig_setup(uint32 connectorIndex, uint32 pixelClock,
// DP PHY to be clocked from external src if possible // DP PHY to be clocked from external src if possible
if (isDP && pll->dpExternalClock) { if (isDP && pll->dpExternalClock) {
// use external clock source // use external clock source
args.v3.acConfig.ucRefClkSource = 2; args.v3.acConfig.ucRefClkSource = ATOM_DCPLL;
} else } else
args.v3.acConfig.ucRefClkSource = pll->id; args.v3.acConfig.ucRefClkSource = pll->id;