ensure framebuffer doesn't exceed PCI bar; add basic monitoring of frame buffer memory allocation; fix return of framebuffer to OS to be the correct area
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@41586 a95241bf-73f2-0310-859d-f6bbb57e9c96
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@ -79,7 +79,8 @@ struct radeon_shared_info {
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addr_t frame_buffer_phys; // card PCI BAR address of FB
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uint32 frame_buffer_int; // card internal offset of FB
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uint32 frame_buffer_size; // card internal FB aperture size
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uint32 frame_buffer_offset; // offset within FB (pri vs sec)
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uint32 frame_buffer_offset; // current offset within FB
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uint32 frame_buffer_free; // free space in framebuffer
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bool has_edid;
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edid1_info edid_info;
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@ -15,7 +15,7 @@
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#undef TRACE
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//#define TRACE_ENGINE
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#define TRACE_ENGINE
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#ifdef TRACE_ENGINE
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# define TRACE(x) _sPrintf x
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#else
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@ -129,6 +129,34 @@ get_color_space_format(const display_mode &mode, uint32 &colorMode,
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}
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uint32
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AllocateFB(uint32 size, const char *description)
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{
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uint32 chunk;
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// TODO : Kernel AreaMapper?
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// Is there any framebuffer left to allocate?
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if (gInfo->shared_info->frame_buffer_free < size) {
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TRACE("%s was unable to allocate a framebuffer - memory shortage\n",
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__func__);
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return 0;
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}
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// assign requested "chunk" of framebuffer memory
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chunk = gInfo->shared_info->frame_buffer_offset;
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// retally framebuffer memory status
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gInfo->shared_info->frame_buffer_offset += size;
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gInfo->shared_info->frame_buffer_free -= size;
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TRACE("%s allocated framebuffer %s at offset 0x%08X (size: 0x%08X)\n",
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__func__, description, chunk, size);
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return chunk;
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}
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// Blacks the screen out, useful for mode setting
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static void
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CardBlankSet(int crtNumber, bool blank)
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@ -165,6 +193,7 @@ CardFBSet(int crtNumber, display_mode *mode)
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write32AtMask(regOffset + gRegister->grphEnable, 1, 0x00000001);
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write32(regOffset + gRegister->grphControl, 0);
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// set color mode on video card
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switch (mode->space) {
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case B_CMAP8:
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write32AtMask(regOffset + gRegister->grphControl,
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@ -190,8 +219,11 @@ CardFBSet(int crtNumber, display_mode *mode)
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// only for chipsets > r600
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// R5xx - RS690 case is GRPH_CONTROL bit 16
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uint32 neededFrameBuffer = mode->timing.h_display
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* bitsPerPixel * mode->virtual_height / 8;
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uint32 fbIntAddress = gInfo->shared_info->frame_buffer_int;
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uint32 fbOffset = gInfo->shared_info->frame_buffer_offset;
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uint32 fbOffset = AllocateFB(neededFrameBuffer, "DisplayFramebuffer");
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write32(regOffset + gRegister->grphPrimarySurfaceAddr,
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fbIntAddress + fbOffset);
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@ -343,11 +375,15 @@ radeon_get_frame_buffer_config(frame_buffer_config *config)
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{
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TRACE("%s\n", __func__);
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uint32 offset = gInfo->shared_info->frame_buffer_offset;
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// TODO : This returns the location of the last allocated fb
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config->frame_buffer = gInfo->shared_info->graphics_memory
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+ gInfo->shared_info->frame_buffer_int
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+ gInfo->shared_info->frame_buffer_offset;
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config->frame_buffer_dma = (uint8 *)gInfo->shared_info->frame_buffer_phys
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+ gInfo->shared_info->frame_buffer_offset;
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config->frame_buffer = gInfo->shared_info->graphics_memory + offset;
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config->frame_buffer_dma
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= (uint8 *)gInfo->shared_info->frame_buffer_phys + offset;
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config->bytes_per_row = gInfo->shared_info->bytes_per_row;
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return B_OK;
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@ -25,6 +25,7 @@
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status_t create_mode_list(void);
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bool is_mode_supported(display_mode* mode);
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status_t is_mode_sane(display_mode *mode);
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uint32 AllocateFB(uint32 size, const char *description);
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#endif /*RADEON_HD_MODE_H*/
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@ -128,6 +128,15 @@ radeon_hd_init(radeon_info &info)
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= read32(info.registers + R6XX_CONFIG_APER_SIZE) / 1024;
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}
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uint32 barSize = info.pci->u.h0.base_register_sizes[RHD_FB_BAR] / 1024;
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// if graphics memory is larger then PCI bar, just map bar
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if (info.shared_info->graphics_memory_size > barSize)
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info.shared_info->frame_buffer_size = barSize;
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else
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info.shared_info->frame_buffer_size
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= info.shared_info->graphics_memory_size;
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int32 memory_size = info.shared_info->graphics_memory_size / 1024;
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int32 frame_buffer_size = info.shared_info->frame_buffer_size / 1024;
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