more cleanup for DMA: re-organised cmd define locations.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@12764 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
parent
c3e79839e0
commit
23f40a2345
@ -170,7 +170,7 @@ status_t nv_acc_init_dma()
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{
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/* (first set) */
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ACCW(HT_HANDL_00, (0x80000000 | NV4_SURFACE)); /* 32bit handle */
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ACCW(HT_VALUE_00, 0x8001114b); /* instance $114b, engine = acc engine, CHID = $00 */
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ACCW(HT_VALUE_00, 0x80011145); /* instance $1145, engine = acc engine, CHID = $00 */
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ACCW(HT_HANDL_01, (0x80000000 | NV_IMAGE_BLIT)); /* 32bit handle */
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ACCW(HT_VALUE_01, 0x80011146); /* instance $1146, engine = acc engine, CHID = $00 */
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@ -179,7 +179,7 @@ status_t nv_acc_init_dma()
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ACCW(HT_VALUE_02, 0x80011147); /* instance $1147, engine = acc engine, CHID = $00 */
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ACCW(HT_HANDL_03, (0x80000000 | NV4_CONTEXT_SURFACES_ARGB_ZS)); /* 32bit handle (3D) */
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ACCW(HT_VALUE_03, 0x8001114c); /* instance $114c, engine = acc engine, CHID = $00 */
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ACCW(HT_VALUE_03, 0x80011148); /* instance $1148, engine = acc engine, CHID = $00 */
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/* NV4_ and NV10_DX5_TEXTURE_TRIANGLE should be identical */
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ACCW(HT_HANDL_04, (0x80000000 | NV4_DX5_TEXTURE_TRIANGLE)); /* 32bit handle (3D) */
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@ -190,7 +190,7 @@ status_t nv_acc_init_dma()
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ACCW(HT_VALUE_05, 0x8001114a); /* instance $114a, engine = acc engine, CHID = $00 */
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ACCW(HT_HANDL_06, (0x80000000 | NV1_RENDER_SOLID_LIN)); /* 32bit handle (not used) */
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ACCW(HT_VALUE_06, 0x80011150); /* instance $1150, engine = acc engine, CHID = $00 */
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ACCW(HT_VALUE_06, 0x8001114b); /* instance $114b, engine = acc engine, CHID = $00 */
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/* (second set) */
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ACCW(HT_HANDL_10, (0x80000000 | NV_ROP5_SOLID)); /* 32bit handle */
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@ -302,6 +302,20 @@ status_t nv_acc_init_dma()
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ACCW(PR_CTX1_2, 0x00000002); /* colorspace not set, notify instance is $0200 (b16-31) */
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ACCW(PR_CTX2_2, 0x00000000); /* DMA0 and DMA1 instance invalid */
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ACCW(PR_CTX3_2, 0x00000000); /* method traps disabled */
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/* setup set '3' for ... */
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if(si->ps.card_arch >= NV10A)
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{
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/* ... cmd NV10_CONTEXT_SURFACES_2D */
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ACCW(PR_CTX0_3, 0x01008062); /* NVclass $062, nv10+: little endian */
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}
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else
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{
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/* ... cmd NV4_SURFACE */
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ACCW(PR_CTX0_3, 0x01008042); /* NVclass $042, nv10+: little endian */
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}
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ACCW(PR_CTX1_3, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */
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ACCW(PR_CTX2_3, 0x11401140); /* DMA0 instance is $1140, DMA1 instance invalid */
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ACCW(PR_CTX3_3, 0x00000000); /* method trap 0 is $1140, trap 1 disabled */
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/* setup set '4' for cmd NV_IMAGE_BLIT */
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ACCW(PR_CTX0_4, 0x0100805f); /* NVclass $05f, patchcfg ROP_AND, nv10+: little endian */
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ACCW(PR_CTX1_4, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */
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@ -312,6 +326,20 @@ status_t nv_acc_init_dma()
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ACCW(PR_CTX1_5, 0x00000002); /* colorspace not set, notify instance is $0200 (b16-31) */
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ACCW(PR_CTX2_5, 0x00000000); /* DMA0 and DMA1 instance invalid */
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ACCW(PR_CTX3_5, 0x00000000); /* method traps disabled */
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/* setup set '6' ... */
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if (si->ps.card_arch != NV04A)
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{
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/* ... for cmd NV10_CONTEXT_SURFACES_ARGB_ZS */
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ACCW(PR_CTX0_6, 0x00000093); /* NVclass $093, nv10+: little endian */
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}
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else
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{
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/* ... for cmd NV4_CONTEXT_SURFACES_ARGB_ZS */
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ACCW(PR_CTX0_6, 0x00000053); /* NVclass $053, nv10+: little endian */
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}
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ACCW(PR_CTX1_6, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */
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ACCW(PR_CTX2_6, 0x11401140); /* DMA0, DMA1 instance = $1140 */
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ACCW(PR_CTX3_6, 0x00000000); /* method traps disabled */
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/* setup set '7' ... */
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if (si->ps.card_arch != NV04A)
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{
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@ -344,47 +372,19 @@ status_t nv_acc_init_dma()
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ACCW(PR_CTX1_8, 0x00000d01); /* format is A8RGB24, MSB mono */
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ACCW(PR_CTX2_8, 0x11401140); /* DMA0, DMA1 instance = $1140 */
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ACCW(PR_CTX3_8, 0x00000000); /* method traps disabled */
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/* setup set '9' for ... */
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if(si->ps.card_arch >= NV10A)
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{
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/* ... cmd NV10_CONTEXT_SURFACES_2D */
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ACCW(PR_CTX0_9, 0x01008062); /* NVclass $062, nv10+: little endian */
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}
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else
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{
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/* ... cmd NV4_SURFACE */
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ACCW(PR_CTX0_9, 0x01008042); /* NVclass $042, nv10+: little endian */
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}
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ACCW(PR_CTX1_9, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */
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ACCW(PR_CTX2_9, 0x11401140); /* DMA0 instance is $1140, DMA1 instance invalid */
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ACCW(PR_CTX3_9, 0x00000000); /* method trap 0 is $1140, trap 1 disabled */
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/* setup set 'A' ... */
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if (si->ps.card_arch != NV04A)
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{
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/* ... for cmd NV10_CONTEXT_SURFACES_ARGB_ZS */
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ACCW(PR_CTX0_A, 0x00000093); /* NVclass $093, nv10+: little endian */
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}
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else
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{
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/* ... for cmd NV04_CONTEXT_SURFACES_ARGB_ZS */
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ACCW(PR_CTX0_A, 0x00000053); /* NVclass $053, nv10+: little endian */
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}
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ACCW(PR_CTX1_A, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */
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ACCW(PR_CTX2_A, 0x11401140); /* DMA0, DMA1 instance = $1140 */
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ACCW(PR_CTX3_A, 0x00000000); /* method traps disabled */
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/* setup set 'E' for cmd NV1_RENDER_SOLID_LIN (not used) */
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ACCW(PR_CTX0_E, 0x0300a01c); /* NVclass $01c, patchcfg ROP_AND, userclip enable,
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/* setup set '9' for cmd NV1_RENDER_SOLID_LIN (not used) */
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ACCW(PR_CTX0_9, 0x0300a01c); /* NVclass $01c, patchcfg ROP_AND, userclip enable,
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* context surface0 valid, nv10+: little endian */
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ACCW(PR_CTX1_E, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */
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ACCW(PR_CTX2_E, 0x11401140); /* DMA0, DMA1 instance = $1140 */
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ACCW(PR_CTX3_E, 0x00000000); /* method traps disabled */
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ACCW(PR_CTX1_9, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */
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ACCW(PR_CTX2_9, 0x11401140); /* DMA0, DMA1 instance = $1140 */
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ACCW(PR_CTX3_9, 0x00000000); /* method traps disabled */
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/* setup DMA set pointed at by PF_CACH1_DMAI */
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ACCW(PR_CTX0_10, 0x00003002); /* DMA page table present and of linear type;
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ACCW(PR_CTX0_A, 0x00003002); /* DMA page table present and of linear type;
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* DMA class is $002 (b0-11);
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* DMA target node is NVM (non-volatile memory?)
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* (instead of doing PCI or AGP transfers) */
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ACCW(PR_CTX1_10, 0x00007fff); /* DMA limit: tablesize is 32k bytes */
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ACCW(PR_CTX2_10, (((si->ps.memory_size - 1) & 0xffff8000) | 0x00000002));
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ACCW(PR_CTX1_A, 0x00007fff); /* DMA limit: tablesize is 32k bytes */
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ACCW(PR_CTX2_A, (((si->ps.memory_size - 1) & 0xffff8000) | 0x00000002));
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/* DMA access type is READ_AND_WRITE;
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* table is located at end of cardRAM (b12-31):
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* It's adress needs to be at a 4kb boundary! */
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@ -393,9 +393,9 @@ status_t nv_acc_init_dma()
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if (si->ps.card_type == NV04)
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{
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/* DMA target node is PCI */
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ACCW(PR_CTX0_10, 0x00023002);
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ACCW(PR_CTX0_A, 0x00023002);
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/* point at the DMA buffer via main system memory */
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ACCW(PR_CTX2_10, (ACCR(PR_CTX2_10) +
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ACCW(PR_CTX2_A, (ACCR(PR_CTX2_A) +
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(((uint32)((uint8 *)(si->framebuffer_pci))) & 0xfffff000)));
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}
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@ -426,10 +426,10 @@ status_t nv_acc_init_dma()
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ACCW(STRD_FMT, 0x03020202);
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/* PRAMIN */
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if (si->ps.card_arch == NV04A)
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ACCW(PR_CTX1_A, 0x00000302); /* format is X24Y8, LSB mono */
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ACCW(PR_CTX1_6, 0x00000302); /* format is X24Y8, LSB mono */
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else
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ACCW(PR_CTX1_A, 0x00000000); /* format is invalid */
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ACCW(PR_CTX1_E, 0x00000302); /* format is X24Y8, LSB mono */
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ACCW(PR_CTX1_6, 0x00000000); /* format is invalid */
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ACCW(PR_CTX1_9, 0x00000302); /* format is X24Y8, LSB mono */
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break;
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case B_RGB15_LITTLE:
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/* acc engine */
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@ -442,8 +442,8 @@ status_t nv_acc_init_dma()
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ACCW(BPIXEL, 0x00000042);
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ACCW(STRD_FMT, 0x09080808);
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/* PRAMIN */
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ACCW(PR_CTX1_A, 0x00000902); /* format is X17RGB15, LSB mono */
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ACCW(PR_CTX1_E, 0x00000902); /* format is X17RGB15, LSB mono */
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ACCW(PR_CTX1_6, 0x00000902); /* format is X17RGB15, LSB mono */
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ACCW(PR_CTX1_9, 0x00000902); /* format is X17RGB15, LSB mono */
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break;
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case B_RGB16_LITTLE:
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/* acc engine */
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@ -459,8 +459,8 @@ status_t nv_acc_init_dma()
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else
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ACCW(STRD_FMT, 0x000b0b0c);
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/* PRAMIN */
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ACCW(PR_CTX1_A, 0x00000c02); /* format is X16RGB16, LSB mono */
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ACCW(PR_CTX1_E, 0x00000c02); /* format is X16RGB16, LSB mono */
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ACCW(PR_CTX1_6, 0x00000c02); /* format is X16RGB16, LSB mono */
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ACCW(PR_CTX1_9, 0x00000c02); /* format is X16RGB16, LSB mono */
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break;
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case B_RGB32_LITTLE:
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case B_RGBA32_LITTLE:
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@ -474,8 +474,8 @@ status_t nv_acc_init_dma()
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ACCW(BPIXEL, 0x000000e7);
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ACCW(STRD_FMT, 0x0e0d0d0d);
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/* PRAMIN */
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ACCW(PR_CTX1_A, 0x00000e02); /* format is X8RGB24, LSB mono */
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ACCW(PR_CTX1_E, 0x00000e02); /* format is X8RGB24, LSB mono */
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ACCW(PR_CTX1_6, 0x00000e02); /* format is X8RGB24, LSB mono */
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ACCW(PR_CTX1_9, 0x00000e02); /* format is X8RGB24, LSB mono */
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break;
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default:
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LOG(8,("ACC: init, invalid bit depth\n"));
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@ -782,7 +782,7 @@ status_t nv_acc_init_dma()
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if (si->ps.card_arch >= NV40A)
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ACCW(PF_CACH1_DMAI, 0x0000114e);
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else
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ACCW(PF_CACH1_DMAI, 0x00001152);
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ACCW(PF_CACH1_DMAI, 0x0000114c);
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/* cache0 push0 access disabled */
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ACCW(PF_CACH0_PSH0, 0x00000000);
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/* cache0 pull0 access disabled */
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