From 23f40a23452a0e9aace1e2abec35db92c73495f4 Mon Sep 17 00:00:00 2001 From: Rudolf Cornelissen Date: Sun, 22 May 2005 13:22:52 +0000 Subject: [PATCH] more cleanup for DMA: re-organised cmd define locations. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@12764 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- .../accelerants/nvidia/engine/nv_acc_dma.c | 102 +++++++++--------- 1 file changed, 51 insertions(+), 51 deletions(-) diff --git a/src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c b/src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c index ea2ef8020e..fb61f371da 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c @@ -170,7 +170,7 @@ status_t nv_acc_init_dma() { /* (first set) */ ACCW(HT_HANDL_00, (0x80000000 | NV4_SURFACE)); /* 32bit handle */ - ACCW(HT_VALUE_00, 0x8001114b); /* instance $114b, engine = acc engine, CHID = $00 */ + ACCW(HT_VALUE_00, 0x80011145); /* instance $1145, engine = acc engine, CHID = $00 */ ACCW(HT_HANDL_01, (0x80000000 | NV_IMAGE_BLIT)); /* 32bit handle */ ACCW(HT_VALUE_01, 0x80011146); /* instance $1146, engine = acc engine, CHID = $00 */ @@ -179,7 +179,7 @@ status_t nv_acc_init_dma() ACCW(HT_VALUE_02, 0x80011147); /* instance $1147, engine = acc engine, CHID = $00 */ ACCW(HT_HANDL_03, (0x80000000 | NV4_CONTEXT_SURFACES_ARGB_ZS)); /* 32bit handle (3D) */ - ACCW(HT_VALUE_03, 0x8001114c); /* instance $114c, engine = acc engine, CHID = $00 */ + ACCW(HT_VALUE_03, 0x80011148); /* instance $1148, engine = acc engine, CHID = $00 */ /* NV4_ and NV10_DX5_TEXTURE_TRIANGLE should be identical */ ACCW(HT_HANDL_04, (0x80000000 | NV4_DX5_TEXTURE_TRIANGLE)); /* 32bit handle (3D) */ @@ -190,7 +190,7 @@ status_t nv_acc_init_dma() ACCW(HT_VALUE_05, 0x8001114a); /* instance $114a, engine = acc engine, CHID = $00 */ ACCW(HT_HANDL_06, (0x80000000 | NV1_RENDER_SOLID_LIN)); /* 32bit handle (not used) */ - ACCW(HT_VALUE_06, 0x80011150); /* instance $1150, engine = acc engine, CHID = $00 */ + ACCW(HT_VALUE_06, 0x8001114b); /* instance $114b, engine = acc engine, CHID = $00 */ /* (second set) */ ACCW(HT_HANDL_10, (0x80000000 | NV_ROP5_SOLID)); /* 32bit handle */ @@ -302,6 +302,20 @@ status_t nv_acc_init_dma() ACCW(PR_CTX1_2, 0x00000002); /* colorspace not set, notify instance is $0200 (b16-31) */ ACCW(PR_CTX2_2, 0x00000000); /* DMA0 and DMA1 instance invalid */ ACCW(PR_CTX3_2, 0x00000000); /* method traps disabled */ + /* setup set '3' for ... */ + if(si->ps.card_arch >= NV10A) + { + /* ... cmd NV10_CONTEXT_SURFACES_2D */ + ACCW(PR_CTX0_3, 0x01008062); /* NVclass $062, nv10+: little endian */ + } + else + { + /* ... cmd NV4_SURFACE */ + ACCW(PR_CTX0_3, 0x01008042); /* NVclass $042, nv10+: little endian */ + } + ACCW(PR_CTX1_3, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */ + ACCW(PR_CTX2_3, 0x11401140); /* DMA0 instance is $1140, DMA1 instance invalid */ + ACCW(PR_CTX3_3, 0x00000000); /* method trap 0 is $1140, trap 1 disabled */ /* setup set '4' for cmd NV_IMAGE_BLIT */ ACCW(PR_CTX0_4, 0x0100805f); /* NVclass $05f, patchcfg ROP_AND, nv10+: little endian */ ACCW(PR_CTX1_4, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */ @@ -312,6 +326,20 @@ status_t nv_acc_init_dma() ACCW(PR_CTX1_5, 0x00000002); /* colorspace not set, notify instance is $0200 (b16-31) */ ACCW(PR_CTX2_5, 0x00000000); /* DMA0 and DMA1 instance invalid */ ACCW(PR_CTX3_5, 0x00000000); /* method traps disabled */ + /* setup set '6' ... */ + if (si->ps.card_arch != NV04A) + { + /* ... for cmd NV10_CONTEXT_SURFACES_ARGB_ZS */ + ACCW(PR_CTX0_6, 0x00000093); /* NVclass $093, nv10+: little endian */ + } + else + { + /* ... for cmd NV4_CONTEXT_SURFACES_ARGB_ZS */ + ACCW(PR_CTX0_6, 0x00000053); /* NVclass $053, nv10+: little endian */ + } + ACCW(PR_CTX1_6, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */ + ACCW(PR_CTX2_6, 0x11401140); /* DMA0, DMA1 instance = $1140 */ + ACCW(PR_CTX3_6, 0x00000000); /* method traps disabled */ /* setup set '7' ... */ if (si->ps.card_arch != NV04A) { @@ -344,47 +372,19 @@ status_t nv_acc_init_dma() ACCW(PR_CTX1_8, 0x00000d01); /* format is A8RGB24, MSB mono */ ACCW(PR_CTX2_8, 0x11401140); /* DMA0, DMA1 instance = $1140 */ ACCW(PR_CTX3_8, 0x00000000); /* method traps disabled */ - /* setup set '9' for ... */ - if(si->ps.card_arch >= NV10A) - { - /* ... cmd NV10_CONTEXT_SURFACES_2D */ - ACCW(PR_CTX0_9, 0x01008062); /* NVclass $062, nv10+: little endian */ - } - else - { - /* ... cmd NV4_SURFACE */ - ACCW(PR_CTX0_9, 0x01008042); /* NVclass $042, nv10+: little endian */ - } - ACCW(PR_CTX1_9, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */ - ACCW(PR_CTX2_9, 0x11401140); /* DMA0 instance is $1140, DMA1 instance invalid */ - ACCW(PR_CTX3_9, 0x00000000); /* method trap 0 is $1140, trap 1 disabled */ - /* setup set 'A' ... */ - if (si->ps.card_arch != NV04A) - { - /* ... for cmd NV10_CONTEXT_SURFACES_ARGB_ZS */ - ACCW(PR_CTX0_A, 0x00000093); /* NVclass $093, nv10+: little endian */ - } - else - { - /* ... for cmd NV04_CONTEXT_SURFACES_ARGB_ZS */ - ACCW(PR_CTX0_A, 0x00000053); /* NVclass $053, nv10+: little endian */ - } - ACCW(PR_CTX1_A, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */ - ACCW(PR_CTX2_A, 0x11401140); /* DMA0, DMA1 instance = $1140 */ - ACCW(PR_CTX3_A, 0x00000000); /* method traps disabled */ - /* setup set 'E' for cmd NV1_RENDER_SOLID_LIN (not used) */ - ACCW(PR_CTX0_E, 0x0300a01c); /* NVclass $01c, patchcfg ROP_AND, userclip enable, + /* setup set '9' for cmd NV1_RENDER_SOLID_LIN (not used) */ + ACCW(PR_CTX0_9, 0x0300a01c); /* NVclass $01c, patchcfg ROP_AND, userclip enable, * context surface0 valid, nv10+: little endian */ - ACCW(PR_CTX1_E, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */ - ACCW(PR_CTX2_E, 0x11401140); /* DMA0, DMA1 instance = $1140 */ - ACCW(PR_CTX3_E, 0x00000000); /* method traps disabled */ + ACCW(PR_CTX1_9, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */ + ACCW(PR_CTX2_9, 0x11401140); /* DMA0, DMA1 instance = $1140 */ + ACCW(PR_CTX3_9, 0x00000000); /* method traps disabled */ /* setup DMA set pointed at by PF_CACH1_DMAI */ - ACCW(PR_CTX0_10, 0x00003002); /* DMA page table present and of linear type; + ACCW(PR_CTX0_A, 0x00003002); /* DMA page table present and of linear type; * DMA class is $002 (b0-11); * DMA target node is NVM (non-volatile memory?) * (instead of doing PCI or AGP transfers) */ - ACCW(PR_CTX1_10, 0x00007fff); /* DMA limit: tablesize is 32k bytes */ - ACCW(PR_CTX2_10, (((si->ps.memory_size - 1) & 0xffff8000) | 0x00000002)); + ACCW(PR_CTX1_A, 0x00007fff); /* DMA limit: tablesize is 32k bytes */ + ACCW(PR_CTX2_A, (((si->ps.memory_size - 1) & 0xffff8000) | 0x00000002)); /* DMA access type is READ_AND_WRITE; * table is located at end of cardRAM (b12-31): * It's adress needs to be at a 4kb boundary! */ @@ -393,9 +393,9 @@ status_t nv_acc_init_dma() if (si->ps.card_type == NV04) { /* DMA target node is PCI */ - ACCW(PR_CTX0_10, 0x00023002); + ACCW(PR_CTX0_A, 0x00023002); /* point at the DMA buffer via main system memory */ - ACCW(PR_CTX2_10, (ACCR(PR_CTX2_10) + + ACCW(PR_CTX2_A, (ACCR(PR_CTX2_A) + (((uint32)((uint8 *)(si->framebuffer_pci))) & 0xfffff000))); } @@ -426,10 +426,10 @@ status_t nv_acc_init_dma() ACCW(STRD_FMT, 0x03020202); /* PRAMIN */ if (si->ps.card_arch == NV04A) - ACCW(PR_CTX1_A, 0x00000302); /* format is X24Y8, LSB mono */ + ACCW(PR_CTX1_6, 0x00000302); /* format is X24Y8, LSB mono */ else - ACCW(PR_CTX1_A, 0x00000000); /* format is invalid */ - ACCW(PR_CTX1_E, 0x00000302); /* format is X24Y8, LSB mono */ + ACCW(PR_CTX1_6, 0x00000000); /* format is invalid */ + ACCW(PR_CTX1_9, 0x00000302); /* format is X24Y8, LSB mono */ break; case B_RGB15_LITTLE: /* acc engine */ @@ -442,8 +442,8 @@ status_t nv_acc_init_dma() ACCW(BPIXEL, 0x00000042); ACCW(STRD_FMT, 0x09080808); /* PRAMIN */ - ACCW(PR_CTX1_A, 0x00000902); /* format is X17RGB15, LSB mono */ - ACCW(PR_CTX1_E, 0x00000902); /* format is X17RGB15, LSB mono */ + ACCW(PR_CTX1_6, 0x00000902); /* format is X17RGB15, LSB mono */ + ACCW(PR_CTX1_9, 0x00000902); /* format is X17RGB15, LSB mono */ break; case B_RGB16_LITTLE: /* acc engine */ @@ -459,8 +459,8 @@ status_t nv_acc_init_dma() else ACCW(STRD_FMT, 0x000b0b0c); /* PRAMIN */ - ACCW(PR_CTX1_A, 0x00000c02); /* format is X16RGB16, LSB mono */ - ACCW(PR_CTX1_E, 0x00000c02); /* format is X16RGB16, LSB mono */ + ACCW(PR_CTX1_6, 0x00000c02); /* format is X16RGB16, LSB mono */ + ACCW(PR_CTX1_9, 0x00000c02); /* format is X16RGB16, LSB mono */ break; case B_RGB32_LITTLE: case B_RGBA32_LITTLE: @@ -474,8 +474,8 @@ status_t nv_acc_init_dma() ACCW(BPIXEL, 0x000000e7); ACCW(STRD_FMT, 0x0e0d0d0d); /* PRAMIN */ - ACCW(PR_CTX1_A, 0x00000e02); /* format is X8RGB24, LSB mono */ - ACCW(PR_CTX1_E, 0x00000e02); /* format is X8RGB24, LSB mono */ + ACCW(PR_CTX1_6, 0x00000e02); /* format is X8RGB24, LSB mono */ + ACCW(PR_CTX1_9, 0x00000e02); /* format is X8RGB24, LSB mono */ break; default: LOG(8,("ACC: init, invalid bit depth\n")); @@ -782,7 +782,7 @@ status_t nv_acc_init_dma() if (si->ps.card_arch >= NV40A) ACCW(PF_CACH1_DMAI, 0x0000114e); else - ACCW(PF_CACH1_DMAI, 0x00001152); + ACCW(PF_CACH1_DMAI, 0x0000114c); /* cache0 push0 access disabled */ ACCW(PF_CACH0_PSH0, 0x00000000); /* cache0 pull0 access disabled */