* Changed the way the device type is tested/set. There shouldn't be any functional
changes. * Minor cleanup. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@32353 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Axel Dörfler
parent
3f6f17cf36
commit
2384335649
@ -1,5 +1,5 @@
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/*
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* Copyright 2006-2008, Haiku, Inc. All Rights Reserved.
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* Copyright 2006-2009, Haiku, Inc. All Rights Reserved.
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* Distributed under the terms of the MIT License.
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*
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* Authors:
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@ -19,20 +19,61 @@
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#define VENDOR_ID_INTEL 0x8086
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#define INTEL_TYPE_FAMILY_MASK 0xf000
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#define INTEL_TYPE_GROUP_MASK 0x0fff
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#define INTEL_TYPE_GROUP_MASK 0xfff0
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#define INTEL_TYPE_MODEL_MASK 0xffff
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// families
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#define INTEL_TYPE_7xx 0x1000
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#define INTEL_TYPE_8xx 0x2000
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#define INTEL_TYPE_9xx 0x4000
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#define INTEL_TYPE_83x (INTEL_TYPE_8xx | 0x0001)
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#define INTEL_TYPE_85x (INTEL_TYPE_8xx | 0x0002)
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#define INTEL_TYPE_91x (INTEL_TYPE_9xx | 0x0010)
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#define INTEL_TYPE_945 (INTEL_TYPE_9xx | 0x0020)
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#define INTEL_TYPE_965 (INTEL_TYPE_9xx | 0x0030)
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#define INTEL_TYPE_G33 (INTEL_TYPE_9xx | 0x0040)
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// groups
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#define INTEL_TYPE_83x (INTEL_TYPE_8xx | 0x0010)
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#define INTEL_TYPE_85x (INTEL_TYPE_8xx | 0x0020)
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#define INTEL_TYPE_91x (INTEL_TYPE_9xx | 0x0040)
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#define INTEL_TYPE_94x (INTEL_TYPE_9xx | 0x0080)
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#define INTEL_TYPE_96x (INTEL_TYPE_9xx | 0x0100)
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#define INTEL_TYPE_Gxx (INTEL_TYPE_9xx | 0x0200)
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// models
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#define INTEL_TYPE_MOBILE 0x0008
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#define INTEL_TYPE_915 (INTEL_TYPE_91x)
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#define INTEL_TYPE_945 (INTEL_TYPE_94x)
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#define INTEL_TYPE_945M (INTEL_TYPE_94x | INTEL_TYPE_MOBILE)
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#define INTEL_TYPE_965 (INTEL_TYPE_96x)
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#define INTEL_TYPE_965M (INTEL_TYPE_96x | INTEL_TYPE_MOBILE)
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#define INTEL_TYPE_G33 (INTEL_TYPE_Gxx)
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#define DEVICE_NAME "intel_extreme"
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#define INTEL_ACCELERANT_NAME "intel_extreme.accelerant"
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struct DeviceType {
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uint32 type;
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DeviceType(int t)
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{
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type = t;
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}
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DeviceType& operator=(int t)
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{
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type = t;
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return *this;
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}
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bool InFamily(uint32 family) const
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{
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return (type & INTEL_TYPE_FAMILY_MASK) == family;
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}
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bool InGroup(uint32 group) const
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{
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return (type & INTEL_TYPE_GROUP_MASK) == group;
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}
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bool IsModel(uint32 model) const
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{
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return (type & INTEL_TYPE_MODEL_MASK) == model;
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}
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};
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// info about PLL on graphics card
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struct pll_info {
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uint32 reference_frequency;
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@ -48,7 +89,7 @@ struct ring_buffer {
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uint32 size;
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uint32 position;
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uint32 space_left;
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uint8 *base;
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uint8* base;
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};
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struct overlay_registers;
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@ -63,9 +104,9 @@ struct intel_shared_info {
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uint32 dpms_mode;
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area_id registers_area; // area of memory mapped registers
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uint8 *status_page;
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uint8* status_page;
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addr_t physical_status_page;
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uint8 *graphics_memory;
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uint8* graphics_memory;
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addr_t physical_graphics_memory;
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uint32 graphics_memory_size;
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@ -86,7 +127,7 @@ struct intel_shared_info {
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bool hardware_cursor_enabled;
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sem_id vblank_sem;
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uint8 *cursor_memory;
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uint8* cursor_memory;
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addr_t physical_cursor_memory;
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uint32 cursor_buffer_offset;
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uint32 cursor_format;
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@ -94,7 +135,7 @@ struct intel_shared_info {
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uint16 cursor_hot_x;
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uint16 cursor_hot_y;
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uint32 device_type;
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DeviceType device_type;
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char device_identifier[32];
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struct pll_info pll_info;
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};
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@ -220,7 +261,7 @@ struct intel_free_graphics_memory {
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#define INTEL_DISPLAY_C_DIGITAL 0x61160
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#define INTEL_DISPLAY_LVDS_PORT 0x61180
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#define LVDS_POST2_RATE_SLOW 14 // PLL Divisors
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#define LVDS_POST2_RATE_FAST 7
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#define LVDS_POST2_RATE_FAST 7
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#define LVDS_CLKB_POWER_MASK (3 << 4)
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#define LVDS_CLKB_POWER_UP (3 << 4)
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#define LVDS_PORT_EN (1 << 31)
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@ -575,19 +616,19 @@ struct overlay_registers {
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inline bool
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intel_uses_physical_overlay(intel_shared_info &info)
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{
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return info.device_type != INTEL_TYPE_G33;
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return !info.device_type.InGroup(INTEL_TYPE_Gxx);
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}
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struct hardware_status {
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uint32 interrupt_status_register;
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uint32 _reserved0[3];
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void *primary_ring_head_storage;
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void* primary_ring_head_storage;
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uint32 _reserved1[3];
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void *secondary_ring_0_head_storage;
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void *secondary_ring_1_head_storage;
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void* secondary_ring_0_head_storage;
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void* secondary_ring_1_head_storage;
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uint32 _reserved2[2];
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void *binning_head_storage;
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void* binning_head_storage;
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uint32 _reserved3[3];
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uint32 store[1008];
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};
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@ -15,7 +15,7 @@ Addon intel_extreme.accelerant :
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memory.cpp
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mode.cpp
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overlay.cpp
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#overlay_3d_i965.cpp
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overlay_3d_i965.cpp
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: be libaccelerantscommon.a
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;
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@ -1,5 +1,5 @@
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/*
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* Copyright 2006-2008, Haiku, Inc. All Rights Reserved.
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* Copyright 2006-2009, Haiku, Inc. All Rights Reserved.
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* Distributed under the terms of the MIT License.
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*
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* Authors:
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@ -34,17 +34,19 @@ struct accelerant_info *gInfo;
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class AreaCloner {
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public:
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AreaCloner();
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~AreaCloner();
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public:
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AreaCloner();
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~AreaCloner();
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area_id Clone(const char *name, void **_address, uint32 spec,
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uint32 protection, area_id sourceArea);
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status_t InitCheck() { return fArea < B_OK ? (status_t)fArea : B_OK; }
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void Keep();
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area_id Clone(const char *name, void **_address,
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uint32 spec, uint32 protection,
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area_id sourceArea);
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status_t InitCheck()
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{ return fArea < 0 ? (status_t)fArea : B_OK; }
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void Keep();
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private:
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area_id fArea;
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private:
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area_id fArea;
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};
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@ -57,12 +59,12 @@ AreaCloner::AreaCloner()
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AreaCloner::~AreaCloner()
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{
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if (fArea >= B_OK)
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if (fArea >= 0)
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delete_area(fArea);
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}
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area_id
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area_id
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AreaCloner::Clone(const char *name, void **_address, uint32 spec,
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uint32 protection, area_id sourceArea)
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{
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@ -71,7 +73,7 @@ AreaCloner::Clone(const char *name, void **_address, uint32 spec,
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}
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void
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void
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AreaCloner::Keep()
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{
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fArea = -1;
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@ -139,7 +141,7 @@ init_common(int device, bool isClone)
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(gInfo->shared_info->graphics_memory
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+ gInfo->shared_info->overlay_offset);
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if (gInfo->shared_info->device_type == INTEL_TYPE_965) {
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if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_96x)) {
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// allocate some extra memory for the 3D context
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if (intel_allocate_memory(INTEL_i965_3D_CONTEXT_SIZE,
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B_APERTURE_NON_RESERVED, gInfo->context_base) == B_OK) {
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@ -181,7 +183,7 @@ intel_init_accelerant(int device)
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TRACE(("intel_init_accelerant()\n"));
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status_t status = init_common(device, false);
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if (status != B_OK)
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if (status != B_OK)
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return status;
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intel_shared_info &info = *gInfo->shared_info;
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@ -203,8 +205,10 @@ intel_init_accelerant(int device)
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uint32 lvds = read32(INTEL_DISPLAY_LVDS_PORT);
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// If we have an enabled display pipe we save the passed information and assume it is the valid panel size..
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// Later we query for proper EDID info if it exists, or figure something else out. (Default modes, etc.)
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// If we have an enabled display pipe we save the passed information and
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// assume it is the valid panel size..
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// Later we query for proper EDID info if it exists, or figure something
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// else out. (Default modes, etc.)
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if ((lvds & DISPLAY_PIPE_ENABLED) != 0) {
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save_lvds_mode();
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gInfo->head_mode |= HEAD_MODE_LVDS_PANEL;
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@ -212,7 +216,8 @@ intel_init_accelerant(int device)
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TRACE(("head detected: %d\n", gInfo->head_mode));
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TRACE(("adpa: %08lx, dova: %08lx, dovb: %08lx, lvds: %08lx\n",
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read32(INTEL_DISPLAY_A_ANALOG_PORT), read32(INTEL_DISPLAY_A_DIGITAL_PORT),
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read32(INTEL_DISPLAY_A_ANALOG_PORT),
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read32(INTEL_DISPLAY_A_DIGITAL_PORT),
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read32(INTEL_DISPLAY_B_DIGITAL_PORT), read32(INTEL_DISPLAY_LVDS_PORT)));
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status = create_mode_list();
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@ -268,7 +273,7 @@ intel_clone_accelerant(void *info)
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status = gInfo->mode_list_area = clone_area(
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"intel extreme cloned modes", (void **)&gInfo->mode_list,
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B_ANY_ADDRESS, B_READ_AREA, gInfo->shared_info->mode_list_area);
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if (status < B_OK)
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if (status < B_OK)
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goto err2;
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return B_OK;
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@ -310,8 +315,7 @@ intel_get_accelerant_device_info(accelerant_device_info *info)
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TRACE(("intel_get_accelerant_device_info()\n"));
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info->version = B_ACCELERANT_VERSION;
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strcpy(info->name,
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(gInfo->shared_info->device_type & INTEL_TYPE_7xx) != 0
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strcpy(info->name, gInfo->shared_info->device_type.InFamily(INTEL_TYPE_7xx)
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? "Intel Extreme Graphics 1" : "Intel Extreme Graphics 2");
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strcpy(info->chipset, gInfo->shared_info->device_identifier);
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strcpy(info->serial_no, "None");
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@ -82,6 +82,8 @@ overlay_token intel_allocate_overlay(void);
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status_t intel_release_overlay(overlay_token overlayToken);
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status_t intel_configure_overlay(overlay_token overlayToken, const overlay_buffer *buffer,
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const overlay_window *window, const overlay_view *view);
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status_t i965_configure_overlay(overlay_token overlayToken, const overlay_buffer *buffer,
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const overlay_window *window, const overlay_view *view);
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#ifdef __cplusplus
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}
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@ -88,7 +88,7 @@ set_i2c_signals(void* cookie, int clock, int data)
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uint32 ioRegister = (uint32)cookie;
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uint32 value;
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if (gInfo->shared_info->device_type == INTEL_TYPE_83x) {
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if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_83x)) {
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// on these chips, the reserved values are fixed
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value = 0;
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} else {
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@ -130,7 +130,7 @@ set_frame_buffer_base()
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surfaceRegister = INTEL_DISPLAY_B_SURFACE;
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}
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if (sharedInfo.device_type == INTEL_TYPE_965) {
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if (sharedInfo.device_type.InGroup(INTEL_TYPE_96x)) {
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write32(baseRegister, mode.v_display_start * sharedInfo.bytes_per_row
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+ mode.h_display_start * (sharedInfo.bits_per_pixel + 7) / 8);
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read32(baseRegister);
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@ -217,7 +217,7 @@ get_pll_limits(pll_limits &limits)
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// Note, the limits are taken from the X driver; they have not yet been
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// tested
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if ((gInfo->shared_info->device_type & INTEL_TYPE_9xx) != 0) {
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if (gInfo->shared_info->device_type.InFamily(INTEL_TYPE_9xx)) {
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// TODO: support LVDS output limits as well
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// (Update: Output limits are adjusted in the computation (post2=7/14))
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// Should move them here!
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@ -356,7 +356,7 @@ save_lvds_mode(void)
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pll_limits limits;
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get_pll_limits(limits);
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if ((gInfo->shared_info->device_type & INTEL_TYPE_9xx) != 0) {
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if (gInfo->shared_info->device_type.InFamily(INTEL_TYPE_9xx)) {
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divisors.post1 = (pll & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK)
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>> DISPLAY_PLL_POST1_DIVISOR_SHIFT;
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@ -596,7 +596,7 @@ if (first) {
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write32(INTEL_VGA_DISPLAY_CONTROL, VGA_DISPLAY_DISABLED);
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read32(INTEL_VGA_DISPLAY_CONTROL);
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if (gInfo->shared_info->device_type != INTEL_TYPE_85x) {
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if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_85x)) {
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}
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if ((gInfo->head_mode & HEAD_MODE_B_DIGITAL) != 0) {
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@ -604,7 +604,7 @@ if (first) {
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compute_pll_divisors(target, divisors, true);
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uint32 dpll = DISPLAY_PLL_NO_VGA_CONTROL;
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if ((gInfo->shared_info->device_type & INTEL_TYPE_9xx) != 0) {
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if (gInfo->shared_info->device_type.InFamily(INTEL_TYPE_9xx)) {
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dpll |= LVDS_PLL_MODE_LVDS;
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// DPLL mode LVDS for i915+
|
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}
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@ -632,9 +632,12 @@ if (first) {
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if ((dpll & DISPLAY_PLL_ENABLED) != 0) {
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write32(INTEL_DISPLAY_B_PLL_DIVISOR_0,
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(((divisors.n - 2) << DISPLAY_PLL_N_DIVISOR_SHIFT) & DISPLAY_PLL_N_DIVISOR_MASK)
|
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| (((divisors.m1 - 2) << DISPLAY_PLL_M1_DIVISOR_SHIFT) & DISPLAY_PLL_M1_DIVISOR_MASK)
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| (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT) & DISPLAY_PLL_M2_DIVISOR_MASK));
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(((divisors.n - 2) << DISPLAY_PLL_N_DIVISOR_SHIFT)
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& DISPLAY_PLL_N_DIVISOR_MASK)
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| (((divisors.m1 - 2) << DISPLAY_PLL_M1_DIVISOR_SHIFT)
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& DISPLAY_PLL_M1_DIVISOR_MASK)
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| (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT)
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& DISPLAY_PLL_M2_DIVISOR_MASK));
|
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write32(INTEL_DISPLAY_B_PLL, dpll & ~DISPLAY_PLL_ENABLED);
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read32(INTEL_DISPLAY_B_PLL);
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spin(150);
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@ -657,9 +660,12 @@ if (first) {
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read32(INTEL_DISPLAY_LVDS_PORT);
|
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|
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write32(INTEL_DISPLAY_B_PLL_DIVISOR_0,
|
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(((divisors.n - 2) << DISPLAY_PLL_N_DIVISOR_SHIFT) & DISPLAY_PLL_N_DIVISOR_MASK)
|
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| (((divisors.m1 - 2) << DISPLAY_PLL_M1_DIVISOR_SHIFT) & DISPLAY_PLL_M1_DIVISOR_MASK)
|
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| (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT) & DISPLAY_PLL_M2_DIVISOR_MASK));
|
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(((divisors.n - 2) << DISPLAY_PLL_N_DIVISOR_SHIFT)
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& DISPLAY_PLL_N_DIVISOR_MASK)
|
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| (((divisors.m1 - 2) << DISPLAY_PLL_M1_DIVISOR_SHIFT)
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& DISPLAY_PLL_M1_DIVISOR_MASK)
|
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| (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT)
|
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& DISPLAY_PLL_M2_DIVISOR_MASK));
|
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|
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write32(INTEL_DISPLAY_B_PLL, dpll);
|
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read32(INTEL_DISPLAY_B_PLL);
|
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@ -667,7 +673,7 @@ if (first) {
|
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// Wait for the clocks to stabilize
|
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spin(150);
|
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|
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if (gInfo->shared_info->device_type == INTEL_TYPE_965) {
|
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if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_96x)) {
|
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float adjusted = ((referenceClock * divisors.m) / divisors.n)
|
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/ divisors.post;
|
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uint32 pixelMultiply = uint32(adjusted
|
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@ -718,8 +724,9 @@ if (first) {
|
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| (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT) & DISPLAY_PLL_M2_DIVISOR_MASK));
|
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|
||||
uint32 pll = DISPLAY_PLL_ENABLED | DISPLAY_PLL_NO_VGA_CONTROL;
|
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if ((gInfo->shared_info->device_type & INTEL_TYPE_9xx) != 0) {
|
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pll |= ((1 << (divisors.post1 - 1)) << DISPLAY_PLL_POST1_DIVISOR_SHIFT)
|
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if (gInfo->shared_info->device_type.InFamily(INTEL_TYPE_9xx)) {
|
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pll |= ((1 << (divisors.post1 - 1))
|
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<< DISPLAY_PLL_POST1_DIVISOR_SHIFT)
|
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& DISPLAY_PLL_9xx_POST1_DIVISOR_MASK;
|
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// pll |= ((divisors.post1 - 1) << DISPLAY_PLL_POST1_DIVISOR_SHIFT)
|
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// & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK;
|
||||
@ -728,7 +735,7 @@ if (first) {
|
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|
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pll |= DISPLAY_PLL_MODE_ANALOG;
|
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|
||||
if (gInfo->shared_info->device_type == INTEL_TYPE_965)
|
||||
if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_96x))
|
||||
pll |= 6 << DISPLAY_PLL_PULSE_PHASE_SHIFT;
|
||||
} else {
|
||||
if (!divisors.post2_high)
|
||||
@ -834,7 +841,7 @@ intel_get_display_mode(display_mode *_currentMode)
|
||||
pll_limits limits;
|
||||
get_pll_limits(limits);
|
||||
|
||||
if ((gInfo->shared_info->device_type & INTEL_TYPE_9xx) != 0) {
|
||||
if (gInfo->shared_info->device_type.InFamily(INTEL_TYPE_9xx)) {
|
||||
divisors.post1 = (pll & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK)
|
||||
>> DISPLAY_PLL_POST1_DIVISOR_SHIFT;
|
||||
|
||||
@ -856,8 +863,10 @@ intel_get_display_mode(display_mode *_currentMode)
|
||||
divisors.m = 5 * divisors.m1 + divisors.m2;
|
||||
divisors.post = divisors.post1 * divisors.post2;
|
||||
|
||||
float referenceClock = gInfo->shared_info->pll_info.reference_frequency / 1000.0f;
|
||||
float pixelClock = ((referenceClock * divisors.m) / divisors.n) / divisors.post;
|
||||
float referenceClock
|
||||
= gInfo->shared_info->pll_info.reference_frequency / 1000.0f;
|
||||
float pixelClock
|
||||
= ((referenceClock * divisors.m) / divisors.n) / divisors.post;
|
||||
|
||||
// timing
|
||||
|
||||
|
||||
@ -227,7 +227,7 @@ static void
|
||||
update_overlay(bool updateCoefficients)
|
||||
{
|
||||
if (!gInfo->shared_info->overlay_active
|
||||
|| gInfo->shared_info->device_type == INTEL_TYPE_965)
|
||||
|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_965))
|
||||
return;
|
||||
|
||||
QueueCommands queue(gInfo->shared_info->primary_ring_buffer);
|
||||
@ -249,7 +249,7 @@ static void
|
||||
show_overlay(void)
|
||||
{
|
||||
if (gInfo->shared_info->overlay_active
|
||||
|| gInfo->shared_info->device_type == INTEL_TYPE_965)
|
||||
|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_965))
|
||||
return;
|
||||
|
||||
gInfo->shared_info->overlay_active = true;
|
||||
@ -269,7 +269,7 @@ static void
|
||||
hide_overlay(void)
|
||||
{
|
||||
if (!gInfo->shared_info->overlay_active
|
||||
|| gInfo->shared_info->device_type == INTEL_TYPE_965)
|
||||
|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_965))
|
||||
return;
|
||||
|
||||
overlay_registers *registers = gInfo->overlay_registers;
|
||||
@ -315,7 +315,7 @@ intel_overlay_supported_spaces(const display_mode *mode)
|
||||
static const uint32 kSupportedi965Spaces[] = {B_YCbCr422, 0};
|
||||
intel_shared_info &sharedInfo = *gInfo->shared_info;
|
||||
|
||||
if (sharedInfo.device_type == INTEL_TYPE_965)
|
||||
if (sharedInfo.device_type.InGroup(INTEL_TYPE_96x))
|
||||
return kSupportedi965Spaces;
|
||||
|
||||
return kSupportedSpaces;
|
||||
@ -368,7 +368,7 @@ intel_allocate_overlay_buffer(color_space colorSpace, uint16 width,
|
||||
// alloc graphics mem
|
||||
|
||||
int32 alignment = 0x3f;
|
||||
if (sharedInfo.device_type == INTEL_TYPE_965)
|
||||
if (sharedInfo.device_type.InGroup(INTEL_TYPE_965))
|
||||
alignment = 0xff;
|
||||
|
||||
overlay_buffer *buffer = &overlay->buffer;
|
||||
@ -384,7 +384,7 @@ intel_allocate_overlay_buffer(color_space colorSpace, uint16 width,
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if (sharedInfo.device_type == INTEL_TYPE_965) {
|
||||
if (sharedInfo.device_type.InGroup(INTEL_TYPE_965)) {
|
||||
status = intel_allocate_memory(INTEL_i965_OVERLAY_STATE_SIZE,
|
||||
B_APERTURE_NON_RESERVED, overlay->state_base);
|
||||
if (status < B_OK) {
|
||||
@ -425,7 +425,7 @@ intel_release_overlay_buffer(const overlay_buffer *buffer)
|
||||
hide_overlay();
|
||||
|
||||
intel_free_memory(overlay->buffer_base);
|
||||
if (gInfo->shared_info->device_type == INTEL_TYPE_965)
|
||||
if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_965))
|
||||
intel_free_memory(overlay->state_base);
|
||||
free(overlay);
|
||||
|
||||
@ -600,33 +600,42 @@ intel_configure_overlay(overlay_token overlayToken, const overlay_buffer *buffer
|
||||
|
||||
// we need to offset the overlay view to adapt it to the clipping
|
||||
// (in addition to whatever offset is desired already)
|
||||
left = view->h_start - (int32)((window->h_start - left) * (horizontalScale / 4096.0) + 0.5);
|
||||
top = view->v_start - (int32)((window->v_start - top) * (verticalScale / 4096.0) + 0.5);
|
||||
left = view->h_start - (int32)((window->h_start - left)
|
||||
* (horizontalScale / 4096.0) + 0.5);
|
||||
top = view->v_start - (int32)((window->v_start - top)
|
||||
* (verticalScale / 4096.0) + 0.5);
|
||||
right = view->h_start + view->width;
|
||||
bottom = view->v_start + view->height;
|
||||
|
||||
gInfo->overlay_position_buffer_offset = buffer->bytes_per_row * top
|
||||
+ left * bytesPerPixel;
|
||||
|
||||
// Note: in non-planar mode, you *must* not program the source width/height
|
||||
// UV registers - they must stay cleared, or the chip is doing strange stuff.
|
||||
// On the other hand, you have to program the UV scaling registers, or the
|
||||
// result will be wrong, too.
|
||||
// Note: in non-planar mode, you *must* not program the source
|
||||
// width/height UV registers - they must stay cleared, or the chip is
|
||||
// doing strange stuff.
|
||||
// On the other hand, you have to program the UV scaling registers, or
|
||||
// the result will be wrong, too.
|
||||
registers->source_width_rgb = right - left;
|
||||
registers->source_height_rgb = bottom - top;
|
||||
if ((gInfo->shared_info->device_type & INTEL_TYPE_8xx) != 0) {
|
||||
registers->source_bytes_per_row_rgb = (((overlay->buffer_offset + (view->width << 1)
|
||||
+ 0x1f) >> 5) - (overlay->buffer_offset >> 5) - 1) << 2;
|
||||
if (gInfo->shared_info->device_type.InFamily(INTEL_TYPE_8xx)) {
|
||||
registers->source_bytes_per_row_rgb = (((overlay->buffer_offset
|
||||
+ (view->width << 1) + 0x1f) >> 5)
|
||||
- (overlay->buffer_offset >> 5) - 1) << 2;
|
||||
} else {
|
||||
registers->source_bytes_per_row_rgb = ((((overlay->buffer_offset + (view->width << 1)
|
||||
+ 0x3f) >> 6) - (overlay->buffer_offset >> 6) << 1) - 1) << 2;
|
||||
registers->source_bytes_per_row_rgb = ((((overlay->buffer_offset
|
||||
+ (view->width << 1) + 0x3f) >> 6)
|
||||
- (overlay->buffer_offset >> 6) << 1) - 1) << 2;
|
||||
}
|
||||
|
||||
// horizontal scaling
|
||||
registers->scale_rgb.horizontal_downscale_factor = horizontalScale >> 12;
|
||||
registers->scale_rgb.horizontal_scale_fraction = horizontalScale & 0xfff;
|
||||
registers->scale_uv.horizontal_downscale_factor = horizontalScaleUV >> 12;
|
||||
registers->scale_uv.horizontal_scale_fraction = horizontalScaleUV & 0xfff;
|
||||
registers->scale_rgb.horizontal_downscale_factor
|
||||
= horizontalScale >> 12;
|
||||
registers->scale_rgb.horizontal_scale_fraction
|
||||
= horizontalScale & 0xfff;
|
||||
registers->scale_uv.horizontal_downscale_factor
|
||||
= horizontalScaleUV >> 12;
|
||||
registers->scale_uv.horizontal_scale_fraction
|
||||
= horizontalScaleUV & 0xfff;
|
||||
|
||||
// vertical scaling
|
||||
registers->scale_rgb.vertical_scale_fraction = verticalScale & 0xfff;
|
||||
@ -635,7 +644,8 @@ intel_configure_overlay(overlay_token overlayToken, const overlay_buffer *buffer
|
||||
registers->vertical_scale_uv = verticalScaleUV >> 12;
|
||||
|
||||
TRACE(("scale: h = %ld.%ld, v = %ld.%ld\n", horizontalScale >> 12,
|
||||
horizontalScale & 0xfff, verticalScale >> 12, verticalScale & 0xfff));
|
||||
horizontalScale & 0xfff, verticalScale >> 12,
|
||||
verticalScale & 0xfff));
|
||||
|
||||
if (verticalScale != gInfo->last_vertical_overlay_scale
|
||||
|| horizontalScale != gInfo->last_horizontal_overlay_scale) {
|
||||
@ -646,16 +656,18 @@ intel_configure_overlay(overlay_token overlayToken, const overlay_buffer *buffer
|
||||
update_coefficients(NUM_HORIZONTAL_TAPS, horizontalScale / 4096.0,
|
||||
true, true, coefficients);
|
||||
|
||||
phase_coefficient coefficientsUV[NUM_HORIZONTAL_UV_TAPS * NUM_PHASES];
|
||||
update_coefficients(NUM_HORIZONTAL_UV_TAPS, horizontalScaleUV / 4096.0,
|
||||
true, false, coefficientsUV);
|
||||
phase_coefficient coefficientsUV[
|
||||
NUM_HORIZONTAL_UV_TAPS * NUM_PHASES];
|
||||
update_coefficients(NUM_HORIZONTAL_UV_TAPS,
|
||||
horizontalScaleUV / 4096.0, true, false, coefficientsUV);
|
||||
|
||||
int32 pos = 0;
|
||||
for (int32 i = 0; i < NUM_PHASES; i++) {
|
||||
for (int32 j = 0; j < NUM_HORIZONTAL_TAPS; j++) {
|
||||
registers->horizontal_coefficients_rgb[pos] = coefficients[pos].sign << 15
|
||||
| coefficients[pos].exponent << 12
|
||||
| coefficients[pos].mantissa;
|
||||
registers->horizontal_coefficients_rgb[pos]
|
||||
= coefficients[pos].sign << 15
|
||||
| coefficients[pos].exponent << 12
|
||||
| coefficients[pos].mantissa;
|
||||
pos++;
|
||||
}
|
||||
}
|
||||
@ -663,9 +675,10 @@ intel_configure_overlay(overlay_token overlayToken, const overlay_buffer *buffer
|
||||
pos = 0;
|
||||
for (int32 i = 0; i < NUM_PHASES; i++) {
|
||||
for (int32 j = 0; j < NUM_HORIZONTAL_UV_TAPS; j++) {
|
||||
registers->horizontal_coefficients_uv[pos] = coefficientsUV[pos].sign << 15
|
||||
| coefficientsUV[pos].exponent << 12
|
||||
| coefficientsUV[pos].mantissa;
|
||||
registers->horizontal_coefficients_uv[pos]
|
||||
= coefficientsUV[pos].sign << 15
|
||||
| coefficientsUV[pos].exponent << 12
|
||||
| coefficientsUV[pos].mantissa;
|
||||
pos++;
|
||||
}
|
||||
}
|
||||
@ -683,11 +696,13 @@ intel_configure_overlay(overlay_token overlayToken, const overlay_buffer *buffer
|
||||
|
||||
// program buffer
|
||||
|
||||
registers->buffer_rgb0 = overlay->buffer_offset + gInfo->overlay_position_buffer_offset;
|
||||
registers->buffer_rgb0
|
||||
= overlay->buffer_offset + gInfo->overlay_position_buffer_offset;
|
||||
registers->stride_rgb = buffer->bytes_per_row;
|
||||
|
||||
registers->mirroring_mode = (window->flags & B_OVERLAY_HORIZONTAL_MIRRORING) != 0
|
||||
? OVERLAY_MIRROR_HORIZONTAL : OVERLAY_MIRROR_NORMAL;
|
||||
registers->mirroring_mode
|
||||
= (window->flags & B_OVERLAY_HORIZONTAL_MIRRORING) != 0
|
||||
? OVERLAY_MIRROR_HORIZONTAL : OVERLAY_MIRROR_NORMAL;
|
||||
registers->ycbcr422_order = 0;
|
||||
|
||||
if (!gInfo->shared_info->overlay_active) {
|
||||
|
||||
@ -48,9 +48,9 @@ const struct supported_device {
|
||||
{0x2592, INTEL_TYPE_91x, "i915GM"},
|
||||
{0x2772, INTEL_TYPE_945, "i945G"},
|
||||
{0x27a2, INTEL_TYPE_945, "i945GM"},
|
||||
{0x27ae, INTEL_TYPE_945, "i945GME"},
|
||||
{0x27ae, INTEL_TYPE_945M, "i945GME"},
|
||||
{0x29a2, INTEL_TYPE_965, "i965G"},
|
||||
{0x2a02, INTEL_TYPE_965, "i965GM"},
|
||||
{0x2a02, INTEL_TYPE_965M, "i965GM"},
|
||||
{0x29b2, INTEL_TYPE_G33, "G33G"},
|
||||
{0x29c2, INTEL_TYPE_G33, "Q35G"},
|
||||
{0x29d2, INTEL_TYPE_G33, "Q33G"},
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright 2006-2008, Haiku, Inc. All Rights Reserved.
|
||||
* Copyright 2006-2009, Haiku, Inc. All Rights Reserved.
|
||||
* Distributed under the terms of the MIT License.
|
||||
*
|
||||
* Authors:
|
||||
@ -193,9 +193,9 @@ intel_extreme_init(intel_info &info)
|
||||
|
||||
int fbIndex = 0;
|
||||
int mmioIndex = 1;
|
||||
if ((info.device_type & INTEL_TYPE_9xx) != 0) {
|
||||
// for some reason Intel saw the need to change the order of the mappings
|
||||
// with the introduction of the i9xx family
|
||||
if (info.device_type.InFamily(INTEL_TYPE_9xx)) {
|
||||
// For some reason Intel saw the need to change the order of the
|
||||
// mappings with the introduction of the i9xx family
|
||||
mmioIndex = 0;
|
||||
fbIndex = 2;
|
||||
}
|
||||
@ -263,13 +263,15 @@ intel_extreme_init(intel_info &info)
|
||||
info.shared_info->frame_buffer = 0;
|
||||
info.shared_info->dpms_mode = B_DPMS_ON;
|
||||
|
||||
if ((info.device_type & INTEL_TYPE_9xx) != 0) {
|
||||
if (info.device_type.InFamily(INTEL_TYPE_9xx)) {
|
||||
info.shared_info->pll_info.reference_frequency = 96000; // 96 kHz
|
||||
info.shared_info->pll_info.max_frequency = 400000; // 400 MHz RAM DAC speed
|
||||
info.shared_info->pll_info.max_frequency = 400000;
|
||||
// 400 MHz RAM DAC speed
|
||||
info.shared_info->pll_info.min_frequency = 20000; // 20 MHz
|
||||
} else {
|
||||
info.shared_info->pll_info.reference_frequency = 48000; // 48 kHz
|
||||
info.shared_info->pll_info.max_frequency = 350000; // 350 MHz RAM DAC speed
|
||||
info.shared_info->pll_info.max_frequency = 350000;
|
||||
// 350 MHz RAM DAC speed
|
||||
info.shared_info->pll_info.min_frequency = 25000; // 25 MHz
|
||||
}
|
||||
|
||||
|
||||
@ -21,27 +21,27 @@ struct intel_info {
|
||||
int32 open_count;
|
||||
status_t init_status;
|
||||
int32 id;
|
||||
pci_info *pci;
|
||||
pci_info* pci;
|
||||
addr_t aperture_base;
|
||||
aperture_id aperture;
|
||||
uint8 *registers;
|
||||
uint8* registers;
|
||||
area_id registers_area;
|
||||
struct intel_shared_info *shared_info;
|
||||
struct intel_shared_info* shared_info;
|
||||
area_id shared_area;
|
||||
|
||||
struct overlay_registers *overlay_registers;
|
||||
struct overlay_registers* overlay_registers;
|
||||
|
||||
bool fake_interrupts;
|
||||
|
||||
const char *device_identifier;
|
||||
uint32 device_type;
|
||||
const char* device_identifier;
|
||||
DeviceType device_type;
|
||||
};
|
||||
|
||||
extern status_t intel_free_memory(intel_info &info, addr_t offset);
|
||||
extern status_t intel_allocate_memory(intel_info &info, size_t size,
|
||||
size_t alignment, uint32 flags, addr_t *_offset,
|
||||
addr_t *_physicalBase = NULL);
|
||||
extern status_t intel_extreme_init(intel_info &info);
|
||||
extern void intel_extreme_uninit(intel_info &info);
|
||||
extern status_t intel_free_memory(intel_info& info, addr_t offset);
|
||||
extern status_t intel_allocate_memory(intel_info& info, size_t size,
|
||||
size_t alignment, uint32 flags, addr_t* _offset,
|
||||
addr_t* _physicalBase = NULL);
|
||||
extern status_t intel_extreme_init(intel_info& info);
|
||||
extern void intel_extreme_uninit(intel_info& info);
|
||||
|
||||
#endif /* INTEL_EXTREME_PRIVATE_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user