finalized virtualscreen panning control granularity constraints for VIA HW. Overlay is now completed BTW. Bumped version to 0.16. Next up: 2D acceleration. Hopefully :)
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@14277 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
parent
217024e94c
commit
0d492d2ff8
@ -4,7 +4,7 @@
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Other authors:
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Mark Watson,
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Rudolf Cornelissen 4/2003-5/2004
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Rudolf Cornelissen 4/2003-9/2005
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*/
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#define MODULE_BIT 0x20000000
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@ -55,9 +55,41 @@ void MOVE_CURSOR(uint16 x, uint16 y)
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si->cursor.x = x;
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si->cursor.y = y;
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/* setting up minimum amount to scroll not needed:
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* Nvidia cards can always do pixelprecise panning on both heads */
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h_adjust = 0x00;
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/* set up minimum amount to scroll */
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if (si->dm.flags & DUALHEAD_BITS)
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{
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//fixme for VIA...
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switch(si->dm.space)
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{
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case B_RGB16_LITTLE:
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h_adjust = 0x1f;
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break;
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case B_RGB32_LITTLE:
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h_adjust = 0x0f;
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break;
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default:
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h_adjust = 0x1f;
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break;
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}
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}
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else
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{
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switch(si->dm.space)
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{
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case B_CMAP8:
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h_adjust = 0x07;
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break;
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case B_RGB15_LITTLE:case B_RGB16_LITTLE:
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h_adjust = 0x03;
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break;
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case B_RGB32_LITTLE:
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h_adjust = 0x01;
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break;
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default:
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h_adjust = 0x07;
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break;
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}
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}
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/* adjust h/v_display_start to move cursor onto screen */
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switch (si->dm.flags & DUALHEAD_BITS)
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@ -6,7 +6,7 @@
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Other authors:
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Mark Watson,
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Apsed,
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Rudolf Cornelissen 11/2002-7/2005
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Rudolf Cornelissen 11/2002-9/2005
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*/
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#define MODULE_BIT 0x00200000
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@ -339,28 +339,49 @@ status_t MOVE_DISPLAY(uint16 h_display_start, uint16 v_display_start) {
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LOG(4,("MOVE_DISPLAY: h %d, v %d\n", h_display_start, v_display_start));
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/* nVidia cards support pixelprecise panning on both heads in all modes:
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* No stepping granularity needed! */
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/* VIA CRTC1 handles multiples of 8 for 8bit, 4 for 16bit, 2 for 32 bit
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VIA CRTC2 is yet unknown...
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*/
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/* determine bits used for the colordepth */
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/* reset lower bits, don't return an error! */
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if (si->dm.flags & DUALHEAD_BITS)
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{
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//fixme for VIA...
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switch(si->dm.space)
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{
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case B_RGB16_LITTLE:
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colour_depth=16;
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h_display_start &= ~0x1f;
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break;
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case B_RGB32_LITTLE:
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colour_depth=32;
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h_display_start &= ~0x0f;
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break;
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default:
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LOG(8,("SET:Invalid DH colour depth 0x%08x, should never happen\n", si->dm.space));
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return B_ERROR;
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}
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}
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else
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{
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switch(si->dm.space)
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{
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case B_CMAP8:
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colour_depth=8;
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h_display_start &= ~0x07;
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break;
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case B_RGB15_LITTLE:
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case B_RGB16_LITTLE:
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case B_RGB15_LITTLE: case B_RGB16_LITTLE:
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colour_depth=16;
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break;
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case B_RGB24_LITTLE:
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colour_depth=24;
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h_display_start &= ~0x03;
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break;
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case B_RGB32_LITTLE:
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colour_depth=32;
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h_display_start &= ~0x01;
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break;
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default:
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return B_ERROR;
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}
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}
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/* do not run past end of display */
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switch (si->dm.flags & DUALHEAD_BITS)
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@ -1,6 +1,6 @@
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/* CTRC functionality */
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/* Author:
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Rudolf Cornelissen 11/2002-7/2005
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Rudolf Cornelissen 11/2002-9/2005
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*/
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#define MODULE_BIT 0x00040000
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@ -585,76 +585,27 @@ status_t eng_crtc_set_display_pitch()
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CRTCW(PITCHL, (offset & 0x00ff));
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CRTCW(VTIMEXT_PIT, (((CRTCR(VTIMEXT_PIT)) & 0x1f) | ((offset & 0x0700) >> 3)));
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//test stuff:
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// LOG(2,("CRTC: $32=$%02x, $33=$%02x, $35=$%02x, $36=$%02x\n",
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// (CRTCR(0x32)), (CRTCR(0x33)), (CRTCR(0x35)), (CRTCR(0x36))));
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// LOG(2,("SEQ: $14=$%02x, $15=$%02x, $16=$%02x, $17=$%02x\n",
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// (SEQR(0x14)), (SEQR(0x15)), (SEQR(0x16)), (SEQR(0x17))));
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// LOG(2,("SEQ: $18=$%02x, $19=$%02x, $1a=$%02x, $1b=$%02x\n",
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// (SEQR(0x18)), (SEQR(0x19)), (SEQR(0x1a)), (SEQR(0x1b))));
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// LOG(2,("SEQ: $1c=$%02x, $1d=$%02x, $1e=$%02x, $1f=$%02x\n",
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// (SEQR(0x1c)), (SEQR(0x1d)), (SEQR(0x1e)), (SEQR(0x1f))));
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// LOG(2,("SEQ: $22=$%02x, $23=$%02x, $24=$%02x, $25=$%02x\n",
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// (SEQR(0x22)), (SEQR(0x23)), (SEQR(0x24)), (SEQR(0x25))));
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// LOG(2,("SEQ: $26=$%02x, $27=$%02x, $28=$%02x, $29=$%02x\n",
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// (SEQR(0x26)), (SEQR(0x27)), (SEQR(0x28)), (SEQR(0x29))));
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// LOG(2,("SEQ: $2a=$%02x, $2b=$%02x, $2e=$%02x\n",
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// (SEQR(0x2a)), (SEQR(0x2b)), (SEQR(0x2e))));
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// LOG(2,("SEQ: $44=$%02x, $45=$%02x, $46=$%02x, $47=$%02x\n",
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// (SEQR(0x44)), (SEQR(0x45)), (SEQR(0x46)), (SEQR(0x47))));
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return B_OK;
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}
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status_t eng_crtc_set_display_start(uint32 startadd,uint8 bpp)
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{
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// uint8 temp;
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uint32 timeout = 0;
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LOG(4,("CRTC: setting card RAM to be displayed bpp %d\n", bpp));
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LOG(2,("CRTC: startadd: $%08x\n", startadd));
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LOG(2,("CRTC: frameRAM: $%08x\n", si->framebuffer));
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LOG(2,("CRTC: framebuffer: $%08x\n", si->fbc.frame_buffer));
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/* we might have no retraces during setmode! */
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/* wait 25mS max. for retrace to occur (refresh > 40Hz) */
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// while (((ENG_REG32(RG32_RASTER) & 0x000007ff) < si->dm.timing.v_display) &&
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// (timeout < (25000/10)))
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if (0)
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{
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/* don't snooze much longer or retrace might get missed! */
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snooze(10);
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timeout++;
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}
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/*
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linux:
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vgaHWGetIOBase(hwp);
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vgaIOBase = hwp->IOBase; //3d0 (rud)
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vgaCRIndex = vgaIOBase + 4;
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define VGAOUT16(addr, val) MMIO_OUT16(pVia->MapBase+0x8000, addr, val)
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Base = Base >> 1;
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VGAOUT16(vgaCRIndex, (Base & 0x00ff00) | 0x0c);
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VGAOUT16(vgaCRIndex, ((Base & 0x00ff) << 8) | 0x0d);
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VGAOUT16(vgaCRIndex, ((Base & 0xff0000) >> 8) | 0x34);
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*/
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/* VIA: upto 32Mb RAM can be adressed */
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/* set standard registers */
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/* (VIA: startadress in 16bit words (b1 - b16) */
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CRTCW(FBSTADDL, ((startadd & 0x000001fe) >> 1));
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/* (VIA: startadress in 64bit words (b3 - b16): checked CLE266) */
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CRTCW(FBSTADDL, ((startadd & 0x000001f8) >> 1));
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CRTCW(FBSTADDH, ((startadd & 0x0001fe00) >> 9));
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/* set extended bits: (b17-24) */
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CRTCW(FBSTADDE, ((startadd & 0x01fe0000) >> 17));
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//fixme: findout if VIA supports pixelpanning...
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/* set NV4/NV10 byte adress: (b0 - 1) */
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// ATBW(HORPIXPAN, ((startadd & 0x00000003) << 1));
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/* VIA doesn't support pixelpanning (checked CLE266). */
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return B_OK;
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}
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@ -90,7 +90,7 @@ status_t eng_general_powerup()
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{
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status_t status;
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LOG(1,("POWERUP: Haiku VIA Accelerant 0.15 running.\n"));
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LOG(1,("POWERUP: Haiku VIA Accelerant 0.16 running.\n"));
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/* preset no laptop */
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si->ps.laptop = false;
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