diff --git a/src/add-ons/accelerants/via/Cursor.c b/src/add-ons/accelerants/via/Cursor.c
index f45078d3eb..2b7d86fd15 100644
--- a/src/add-ons/accelerants/via/Cursor.c
+++ b/src/add-ons/accelerants/via/Cursor.c
@@ -4,7 +4,7 @@
 
 	Other authors:
 	Mark Watson,
-	Rudolf Cornelissen 4/2003-5/2004
+	Rudolf Cornelissen 4/2003-9/2005
 */
 
 #define MODULE_BIT 0x20000000
@@ -55,9 +55,41 @@ void MOVE_CURSOR(uint16 x, uint16 y)
 	si->cursor.x = x;
 	si->cursor.y = y;
 
-	/* setting up minimum amount to scroll not needed:
-	 * Nvidia cards can always do pixelprecise panning on both heads */
-	h_adjust = 0x00;
+	/* set up minimum amount to scroll */
+	if (si->dm.flags & DUALHEAD_BITS)
+	{
+		//fixme for VIA...
+		switch(si->dm.space)
+		{
+		case B_RGB16_LITTLE:
+			h_adjust = 0x1f;
+			break;
+		case B_RGB32_LITTLE:
+			h_adjust = 0x0f;
+			break;
+		default:
+			h_adjust = 0x1f;
+			break;
+		}
+	}
+	else
+	{
+		switch(si->dm.space)
+		{
+		case B_CMAP8:
+			h_adjust = 0x07;
+			break;
+		case B_RGB15_LITTLE:case B_RGB16_LITTLE:
+			h_adjust = 0x03;
+			break;
+		case B_RGB32_LITTLE:
+			h_adjust = 0x01;
+			break;
+		default:
+			h_adjust = 0x07;
+			break;
+		}
+	}
 
 	/* adjust h/v_display_start to move cursor onto screen */
 	switch (si->dm.flags & DUALHEAD_BITS)
diff --git a/src/add-ons/accelerants/via/SetDisplayMode.c b/src/add-ons/accelerants/via/SetDisplayMode.c
index 96aac06716..f5b3d79f4f 100644
--- a/src/add-ons/accelerants/via/SetDisplayMode.c
+++ b/src/add-ons/accelerants/via/SetDisplayMode.c
@@ -6,7 +6,7 @@
 	Other authors:
 	Mark Watson,
 	Apsed,
-	Rudolf Cornelissen 11/2002-7/2005
+	Rudolf Cornelissen 11/2002-9/2005
 */
 
 #define MODULE_BIT 0x00200000
@@ -339,27 +339,48 @@ status_t MOVE_DISPLAY(uint16 h_display_start, uint16 v_display_start) {
 
 	LOG(4,("MOVE_DISPLAY: h %d, v %d\n", h_display_start, v_display_start));
 
-	/* nVidia cards support pixelprecise panning on both heads in all modes:
-	 * No stepping granularity needed! */
+	/* VIA CRTC1 handles multiples of 8 for 8bit, 4 for 16bit, 2 for 32 bit 
+	   VIA CRTC2 is yet unknown...
+     */
 
-	/* determine bits used for the colordepth */
-	switch(si->dm.space)
+	/* reset lower bits, don't return an error! */
+	if (si->dm.flags & DUALHEAD_BITS)
 	{
-	case B_CMAP8:
-		colour_depth=8;
-		break;
-	case B_RGB15_LITTLE:
-	case B_RGB16_LITTLE:
-		colour_depth=16;
-		break;
-	case B_RGB24_LITTLE:
-		colour_depth=24;
-		break;
-	case B_RGB32_LITTLE:
-		colour_depth=32;
-		break;
-	default:
-		return B_ERROR;
+		//fixme for VIA...
+		switch(si->dm.space)
+		{
+		case B_RGB16_LITTLE:
+			colour_depth=16;
+			h_display_start &= ~0x1f;
+			break;
+		case B_RGB32_LITTLE:
+			colour_depth=32;
+			h_display_start &= ~0x0f;
+			break;
+		default:
+			LOG(8,("SET:Invalid DH colour depth 0x%08x, should never happen\n", si->dm.space));
+			return B_ERROR;
+		}
+	}
+	else
+	{
+		switch(si->dm.space)
+		{
+		case B_CMAP8:
+			colour_depth=8;
+			h_display_start &= ~0x07;
+			break;
+		case B_RGB15_LITTLE: case B_RGB16_LITTLE:
+			colour_depth=16;
+			h_display_start &= ~0x03;
+			break;
+		case B_RGB32_LITTLE:
+			colour_depth=32;
+			h_display_start &= ~0x01;
+			break;
+		default:
+			return B_ERROR;
+		}
 	}
 
 	/* do not run past end of display */
diff --git a/src/add-ons/accelerants/via/engine/crtc.c b/src/add-ons/accelerants/via/engine/crtc.c
index 45dbfc0173..54de84fdd3 100644
--- a/src/add-ons/accelerants/via/engine/crtc.c
+++ b/src/add-ons/accelerants/via/engine/crtc.c
@@ -1,6 +1,6 @@
 /* CTRC functionality */
 /* Author:
-   Rudolf Cornelissen 11/2002-7/2005
+   Rudolf Cornelissen 11/2002-9/2005
 */
 
 #define MODULE_BIT 0x00040000
@@ -585,76 +585,27 @@ status_t eng_crtc_set_display_pitch()
 	CRTCW(PITCHL, (offset & 0x00ff));
 	CRTCW(VTIMEXT_PIT, (((CRTCR(VTIMEXT_PIT)) & 0x1f) | ((offset & 0x0700) >> 3)));
 
-//test stuff:
-//	LOG(2,("CRTC: $32=$%02x, $33=$%02x, $35=$%02x, $36=$%02x\n",
-//		(CRTCR(0x32)), (CRTCR(0x33)), (CRTCR(0x35)), (CRTCR(0x36))));
-//	LOG(2,("SEQ: $14=$%02x, $15=$%02x, $16=$%02x, $17=$%02x\n",
-//		(SEQR(0x14)), (SEQR(0x15)), (SEQR(0x16)), (SEQR(0x17))));
-//	LOG(2,("SEQ: $18=$%02x, $19=$%02x, $1a=$%02x, $1b=$%02x\n",
-//		(SEQR(0x18)), (SEQR(0x19)), (SEQR(0x1a)), (SEQR(0x1b))));
-//	LOG(2,("SEQ: $1c=$%02x, $1d=$%02x, $1e=$%02x, $1f=$%02x\n",
-//		(SEQR(0x1c)), (SEQR(0x1d)), (SEQR(0x1e)), (SEQR(0x1f))));
-//	LOG(2,("SEQ: $22=$%02x, $23=$%02x, $24=$%02x, $25=$%02x\n",
-//		(SEQR(0x22)), (SEQR(0x23)), (SEQR(0x24)), (SEQR(0x25))));
-//	LOG(2,("SEQ: $26=$%02x, $27=$%02x, $28=$%02x, $29=$%02x\n",
-//		(SEQR(0x26)), (SEQR(0x27)), (SEQR(0x28)), (SEQR(0x29))));
-//	LOG(2,("SEQ: $2a=$%02x, $2b=$%02x, $2e=$%02x\n",
-//		(SEQR(0x2a)), (SEQR(0x2b)), (SEQR(0x2e))));
-//	LOG(2,("SEQ: $44=$%02x, $45=$%02x, $46=$%02x, $47=$%02x\n",
-//		(SEQR(0x44)), (SEQR(0x45)), (SEQR(0x46)), (SEQR(0x47))));
-
 	return B_OK;
 }
 
 status_t eng_crtc_set_display_start(uint32 startadd,uint8 bpp) 
 {
-//	uint8 temp;
-	uint32 timeout = 0;
-
 	LOG(4,("CRTC: setting card RAM to be displayed bpp %d\n", bpp));
 
 	LOG(2,("CRTC: startadd: $%08x\n", startadd));
 	LOG(2,("CRTC: frameRAM: $%08x\n", si->framebuffer));
 	LOG(2,("CRTC: framebuffer: $%08x\n", si->fbc.frame_buffer));
 
-	/* we might have no retraces during setmode! */
-	/* wait 25mS max. for retrace to occur (refresh > 40Hz) */
-//	while (((ENG_REG32(RG32_RASTER) & 0x000007ff) < si->dm.timing.v_display) &&
-//			(timeout < (25000/10)))
-	if (0)
-	{
-		/* don't snooze much longer or retrace might get missed! */
-		snooze(10);
-		timeout++;
-	}
-
-/*
-linux:
-   vgaHWGetIOBase(hwp);
-        vgaIOBase = hwp->IOBase; //3d0 (rud)
-        vgaCRIndex = vgaIOBase + 4;
-
-define VGAOUT16(addr, val) MMIO_OUT16(pVia->MapBase+0x8000, addr, val)
-
-      Base = Base >> 1;
-        VGAOUT16(vgaCRIndex, (Base & 0x00ff00) | 0x0c);
-        VGAOUT16(vgaCRIndex, ((Base & 0x00ff) << 8) | 0x0d);
-        VGAOUT16(vgaCRIndex, ((Base & 0xff0000) >> 8) | 0x34);
-*/
- 
 	/* VIA: upto 32Mb RAM can be adressed */
 
 	/* set standard registers */
-	/* (VIA: startadress in 16bit words (b1 - b16) */
-	CRTCW(FBSTADDL, ((startadd & 0x000001fe) >> 1));
+	/* (VIA: startadress in 64bit words (b3 - b16): checked CLE266) */
+	CRTCW(FBSTADDL, ((startadd & 0x000001f8) >> 1));
 	CRTCW(FBSTADDH, ((startadd & 0x0001fe00) >> 9));
 	/* set extended bits: (b17-24) */
 	CRTCW(FBSTADDE, ((startadd & 0x01fe0000) >> 17));
 
-//fixme: findout if VIA supports pixelpanning...
-
-	/* set NV4/NV10 byte adress: (b0 - 1) */
-//	ATBW(HORPIXPAN, ((startadd & 0x00000003) << 1));
+	/* VIA doesn't support pixelpanning (checked CLE266). */
 
 	return B_OK;
 }
diff --git a/src/add-ons/accelerants/via/engine/general.c b/src/add-ons/accelerants/via/engine/general.c
index 1c1e01575c..c41b2bab31 100644
--- a/src/add-ons/accelerants/via/engine/general.c
+++ b/src/add-ons/accelerants/via/engine/general.c
@@ -90,7 +90,7 @@ status_t eng_general_powerup()
 {
 	status_t status;
 
-	LOG(1,("POWERUP: Haiku VIA Accelerant 0.15 running.\n"));
+	LOG(1,("POWERUP: Haiku VIA Accelerant 0.16 running.\n"));
 
 	/* preset no laptop */
 	si->ps.laptop = false;