XHCI: Rework TRB size handling.
There is a section of the spec that dictates how TRBs need to be sized within a TD, and we were not following that. This should bring us into compliance. See inline comments for more details.
This commit is contained in:
Augustin Cavalier
parent
84fc83275d
commit
0981cb8686
@ -795,44 +795,41 @@ XHCI::SubmitNormalRequest(Transfer *transfer)
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if (status != B_OK)
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return status;
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// Compute the size to use for the TRBs, and then how many TRBs
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// of this size we will need. We always need at least 1, of course.
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size_t dataLength = transfer->DataLength(),
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packetSize = pipe->MaxPacketSize(),
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packetsPerTrb = 4;
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// TRBs within a TD must be "grouped" into TD Fragments, which mostly means
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// that a max_burst_payload boundary cannot be crossed within a TRB, but
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// only between TRBs. More than one TRB can be in a TD Fragment, but we keep
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// things simple by setting trbSize to the MBP. (XHCI 1.2 § 4.11.7.1 p235.)
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size_t trbSize = endpoint->max_burst_payload;
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if (isochronousData != NULL) {
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if (isochronousData->packet_count == 0)
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return B_BAD_VALUE;
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// Isochronous transfers use more specifically sized packets.
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packetSize = transfer->DataLength() / isochronousData->packet_count;
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if (packetSize > pipe->MaxPacketSize() || packetSize
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trbSize = transfer->DataLength() / isochronousData->packet_count;
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if (trbSize > pipe->MaxPacketSize() || trbSize
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!= (size_t)isochronousData->packet_descriptors[0].request_length)
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return B_BAD_VALUE;
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packetsPerTrb = 1;
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}
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// Now that we know packetSize & packetsPerTrb, compute TRB size and count.
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const size_t trbSize = packetsPerTrb * packetSize;
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const int32 trbCount = (dataLength + trbSize - 1) / trbSize;
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// Now that we know trbSize, compute the count.
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const int32 trbCount = (transfer->DataLength() + trbSize - 1) / trbSize;
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xhci_td *td = CreateDescriptor(trbCount, trbCount, trbSize);
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if (td == NULL)
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return B_NO_MEMORY;
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// Normal Stage
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size_t remaining = dataLength;
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int32 remainingPackets = (remaining - trbSize) / packetSize;
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size_t remaining = transfer->DataLength();
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for (int32 i = 0; i < trbCount; i++) {
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// The "TD Size" field of a transfer TRB indicates the number of
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// remaining maximum-size *packets* in this TD, *not* including the
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// packets in the current TRB, and capped at 31 if there are more
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// than 31 packets remaining in the TD. (XHCI 1.2 § 4.11.2.4 p218.)
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int32 tdSize = remainingPackets > 31 ? 31 : remainingPackets;
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if (tdSize < 0)
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tdSize = 0;
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int32 trbLength = remaining < trbSize ? remaining : trbSize;
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int32 tdSize = remaining / pipe->MaxPacketSize();
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if (tdSize > 31)
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tdSize = 31;
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int32 trbLength = (remaining < trbSize) ? remaining : trbSize;
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td->trbs[i].address = td->buffer_addrs[i];
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td->trbs[i].status = TRB_2_IRQ(0)
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@ -844,7 +841,6 @@ XHCI::SubmitNormalRequest(Transfer *transfer)
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td->trb_used++;
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remaining -= trbLength;
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remainingPackets -= packetsPerTrb;
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}
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// Isochronous-specific
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@ -1482,9 +1478,19 @@ XHCI::AllocateDevice(Hub *parent, int8 hubAddress, uint8 hubPort,
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break;
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}
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xhci_endpoint* endpoint0 = &device->endpoints[0];
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mutex_init(&endpoint0->lock, "xhci endpoint lock");
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endpoint0->device = device;
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endpoint0->id = 0;
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endpoint0->td_head = NULL;
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endpoint0->used = 0;
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endpoint0->current = 0;
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endpoint0->trbs = device->trbs;
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endpoint0->trb_addr = device->trb_addr;
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// configure the Control endpoint 0
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if (ConfigureEndpoint(slot, 0, USB_OBJECT_CONTROL_PIPE, false,
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device->trb_addr, 0, maxPacketSize, speed, 0, 0) != B_OK) {
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if (ConfigureEndpoint(endpoint0, slot, 0, USB_OBJECT_CONTROL_PIPE, false,
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0, maxPacketSize, speed, 0, 0) != B_OK) {
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TRACE_ERROR("unable to configure default control endpoint\n");
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delete_area(device->input_ctx_area);
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delete_area(device->device_ctx_area);
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@ -1494,15 +1500,6 @@ XHCI::AllocateDevice(Hub *parent, int8 hubAddress, uint8 hubPort,
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return NULL;
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}
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mutex_init(&device->endpoints[0].lock, "xhci endpoint lock");
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device->endpoints[0].device = device;
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device->endpoints[0].id = 0;
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device->endpoints[0].td_head = NULL;
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device->endpoints[0].used = 0;
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device->endpoints[0].current = 0;
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device->endpoints[0].trbs = device->trbs;
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device->endpoints[0].trb_addr = device->trb_addr;
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// device should get to addressed state (bsr = 0)
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if (SetAddress(device->input_ctx_addr, false, slot) != B_OK) {
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TRACE_ERROR("unable to set address\n");
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@ -1527,7 +1524,7 @@ XHCI::AllocateDevice(Hub *parent, int8 hubAddress, uint8 hubPort,
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// Create a temporary pipe with the new address
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ControlPipe pipe(parent);
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pipe.SetControllerCookie(&device->endpoints[0]);
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pipe.SetControllerCookie(endpoint0);
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pipe.InitCommon(device->address + 1, 0, speed, Pipe::Default, maxPacketSize, 0,
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hubAddress, hubPort);
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@ -1692,7 +1689,7 @@ XHCI::_InsertEndpointForPipe(Pipe *pipe)
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return B_NO_INIT;
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}
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uint8 id = (2 * pipe->EndpointAddress()
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const uint8 id = (2 * pipe->EndpointAddress()
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+ (pipe->Direction() != Pipe::Out ? 1 : 0)) - 1;
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if (id >= XHCI_MAX_ENDPOINTS - 1)
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return B_BAD_VALUE;
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@ -1707,46 +1704,45 @@ XHCI::_InsertEndpointForPipe(Pipe *pipe)
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EvaluateContext(device->input_ctx_addr, device->slot);
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}
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mutex_init(&device->endpoints[id].lock, "xhci endpoint lock");
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MutexLocker endpointLocker(device->endpoints[id].lock);
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xhci_endpoint* endpoint = &device->endpoints[id];
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mutex_init(&endpoint->lock, "xhci endpoint lock");
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MutexLocker endpointLocker(endpoint->lock);
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device->endpoints[id].device = device;
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device->endpoints[id].id = id;
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device->endpoints[id].td_head = NULL;
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device->endpoints[id].used = 0;
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device->endpoints[id].current = 0;
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endpoint->device = device;
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endpoint->id = id;
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endpoint->td_head = NULL;
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endpoint->used = 0;
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endpoint->current = 0;
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device->endpoints[id].trbs = device->trbs
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+ id * XHCI_ENDPOINT_RING_SIZE;
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device->endpoints[id].trb_addr = device->trb_addr
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endpoint->trbs = device->trbs + id * XHCI_ENDPOINT_RING_SIZE;
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endpoint->trb_addr = device->trb_addr
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+ id * XHCI_ENDPOINT_RING_SIZE * sizeof(xhci_trb);
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memset(device->endpoints[id].trbs, 0,
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memset(endpoint->trbs, 0,
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sizeof(xhci_trb) * XHCI_ENDPOINT_RING_SIZE);
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TRACE("_InsertEndpointForPipe trbs device %p endpoint %p\n",
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device->trbs, device->endpoints[id].trbs);
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device->trbs, endpoint->trbs);
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TRACE("_InsertEndpointForPipe trb_addr device 0x%" B_PRIxPHYSADDR
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" endpoint 0x%" B_PRIxPHYSADDR "\n", device->trb_addr,
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device->endpoints[id].trb_addr);
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endpoint->trb_addr);
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uint8 endpoint = id + 1;
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const uint8 endpointNum = id + 1;
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TRACE("trb_addr 0x%" B_PRIxPHYSADDR "\n", device->endpoints[id].trb_addr);
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TRACE("trb_addr 0x%" B_PRIxPHYSADDR "\n", endpoint->trb_addr);
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status_t status = ConfigureEndpoint(device->slot, id, pipe->Type(),
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pipe->Direction() == Pipe::In, device->endpoints[id].trb_addr,
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pipe->Interval(), pipe->MaxPacketSize(), usbDevice->Speed(),
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pipe->MaxBurst(), pipe->BytesPerInterval());
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status_t status = ConfigureEndpoint(endpoint, device->slot, id, pipe->Type(),
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pipe->Direction() == Pipe::In, pipe->Interval(), pipe->MaxPacketSize(),
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usbDevice->Speed(), pipe->MaxBurst(), pipe->BytesPerInterval());
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if (status != B_OK) {
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TRACE_ERROR("unable to configure endpoint\n");
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TRACE_ERROR("unable to configure endpoint: %s\n", strerror(status));
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return status;
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}
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_WriteContext(&device->input_ctx->input.dropFlags, 0);
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_WriteContext(&device->input_ctx->input.addFlags,
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(1 << endpoint) | (1 << 0));
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(1 << endpointNum) | (1 << 0));
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if (endpoint > 1)
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if (endpointNum > 1)
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ConfigureEndpoint(device->input_ctx_addr, false, device->slot);
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else
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EvaluateContext(device->input_ctx_addr, device->slot);
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@ -1980,8 +1976,8 @@ XHCI::_UnlinkDescriptorForPipe(xhci_td *descriptor, xhci_endpoint *endpoint)
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status_t
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XHCI::ConfigureEndpoint(uint8 slot, uint8 number, uint8 type, bool directionIn,
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uint64 ringAddr, uint16 interval, uint16 maxPacketSize, usb_speed speed,
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XHCI::ConfigureEndpoint(xhci_endpoint* ep, uint8 slot, uint8 number, uint8 type,
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bool directionIn, uint16 interval, uint16 maxPacketSize, usb_speed speed,
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uint8 maxBurst, uint16 bytesPerInterval)
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{
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struct xhci_device* device = &fDevices[slot];
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@ -2057,7 +2053,11 @@ XHCI::ConfigureEndpoint(uint8 slot, uint8 number, uint8 type, bool directionIn,
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// Assign maximum packet size, set the ring address, and set the
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// "Dequeue Cycle State" bit. (XHCI 1.2 § 6.2.3 Table 6-10 p453.)
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dwendpoint1 |= ENDPOINT_1_MAXPACKETSIZE(maxPacketSize);
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qwendpoint2 |= ENDPOINT_2_DCS_BIT | ringAddr;
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qwendpoint2 |= ENDPOINT_2_DCS_BIT | ep->trb_addr;
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// The Max Burst Payload is the number of bytes moved by a
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// maximum sized burst. (XHCI 1.2 § 4.11.7.1 p236.)
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ep->max_burst_payload = (maxBurst + 1) * maxPacketSize;
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// Assign average TRB length.
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if ((type & USB_OBJECT_CONTROL_PIPE) != 0) {
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@ -2070,8 +2070,8 @@ XHCI::ConfigureEndpoint(uint8 slot, uint8 number, uint8 type, bool directionIn,
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// but we don't know what it is here.)
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dwendpoint4 |= ENDPOINT_4_AVGTRBLENGTH(maxPacketSize);
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} else {
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// Under all other circumstances, we put 4 packets in a TRB.
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dwendpoint4 |= ENDPOINT_4_AVGTRBLENGTH(maxPacketSize * 4);
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// Under all other circumstances, we put max_burst_payload in a TRB.
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dwendpoint4 |= ENDPOINT_4_AVGTRBLENGTH(ep->max_burst_payload);
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}
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// Assign maximum ESIT payload. (XHCI 1.2 § 4.14.2 p259.)
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@ -62,6 +62,8 @@ typedef struct xhci_endpoint {
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xhci_device* device;
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uint8 id;
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uint16 max_burst_payload;
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xhci_td* td_head;
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uint8 used;
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uint8 current;
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@ -137,8 +139,8 @@ private:
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int32 Interrupt();
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// Endpoint management
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status_t ConfigureEndpoint(uint8 slot, uint8 number,
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uint8 type, bool directionIn, uint64 ringAddr,
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status_t ConfigureEndpoint(xhci_endpoint* ep, uint8 slot,
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uint8 number, uint8 type, bool directionIn,
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uint16 interval, uint16 maxPacketSize,
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usb_speed speed, uint8 maxBurst,
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uint16 bytesPerInterval);
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