coldstart updates, the driver now looks at the 'usebios' setting. still no actual execution though.
git-svn-id: file:///srv/svn/repos/haiku/trunk/current@8658 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
parent
7fd612e59f
commit
03fb171873
@ -1,7 +1,7 @@
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/* Authors:
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Mark Watson 12/1999,
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Apsed,
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Rudolf Cornelissen 10/2002-7/2004
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Rudolf Cornelissen 10/2002-8/2004
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*/
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#define MODULE_BIT 0x00008000
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@ -80,7 +80,7 @@ status_t nv_general_powerup()
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{
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status_t status;
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LOG(1,("POWERUP: nVidia (open)BeOS Accelerant 0.23 running.\n"));
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LOG(1,("POWERUP: nVidia (open)BeOS Accelerant 0.24 running.\n"));
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/* preset no laptop */
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si->ps.laptop = false;
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@ -781,115 +781,36 @@ void set_crtc_owner(bool head)
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static status_t nvxx_general_powerup()
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{
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status_t result;
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LOG(4, ("INIT: NV powerup\n"));
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if (si->settings.logmask & 0x80000000) nv_dump_configuration_space();
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/* initialize the shared_info PINS struct */
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result = parse_pins();
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// if (result != B_OK) fake_pins();
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//temporary:
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/* fill-in the cardspecs in the shared_info PINS struct */
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fake_pins();
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/* log the PINS struct settings */
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/* only process BIOS for specs and coldstart if requested by user;
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* note:
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* this in fact frees the driver from relying on the BIOS to be executed
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* at system power-up POST time. */
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if (!si->settings.usebios)
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{
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LOG(2, ("INIT: Attempting card coldstart!\n"));
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/* update the cardspecs in the shared_info PINS struct according to reported
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* specs as much as is possible;
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* this also coldstarts the card if possible (executes BIOS CMD script(s)) */
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parse_pins();
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}
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else
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{
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LOG(2, ("INIT: Skipping card coldstart!\n"));
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}
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/* log the final PINS struct settings */
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dump_pins();
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/* setup CRTC and DAC functions access: determined in parse_pins/fake_pins */
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/* setup CRTC and DAC functions access: determined in fake_pins */
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setup_virtualized_heads(si->ps.crtc2_prim);
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/* if the user doesn't want a coldstart OR the BIOS pins info could not be found warmstart */
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//temp:
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return nv_general_bios_to_powergraphics();
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if (si->settings.usebios || (result != B_OK)) return nv_general_bios_to_powergraphics();
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/*power up the PLLs,LUT,DAC*/
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LOG(2,("INIT: PLL/LUT/DAC powerup\n"));
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/* turn off both displays and the hardcursors (also disables transfers) */
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head1_dpms(false, false, false);
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head1_cursor_hide();
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if (si->ps.secondary_head)
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{
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head2_dpms(false, false, false);
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head2_cursor_hide();
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}
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/* G200 SGRAM and SDRAM use external pix and dac refs, do *not* activate internals!
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* (this would create electrical shortcuts,
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* resulting in extra chip heat and distortions visible on screen */
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/* set voltage reference - using DAC reference block partly */
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// DXIW(VREFCTRL,0x03);
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/* wait for 100ms for voltage reference to stabilize */
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delay(100000);
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/* power up the SYSPLL */
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// CFGW(OPTION,CFGR(OPTION)|0x20);
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/* power up the PIXPLL */
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// DXIW(PIXCLKCTRL,0x08);
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/* disable pixelclock oscillations before switching on CLUT */
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// DXIW(PIXCLKCTRL, (DXIR(PIXCLKCTRL) | 0x04));
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/* disable 15bit mode CLUT-overlay function */
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// DXIW(GENCTRL, DXIR(GENCTRL & 0xfd));
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/* CRTC2->MAFC, 8-bit DAC, CLUT enabled, enable DAC */
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// DXIW(MISCCTRL,0x1b);
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snooze(250);
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/* re-enable pixelclock oscillations */
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// DXIW(PIXCLKCTRL, (DXIR(PIXCLKCTRL) & 0xfb));
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/* setup i2c bus */
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i2c_init();
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/*make sure card is in powergraphics mode*/
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// VGAW_I(CRTCEXT,3,0x80);
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/*set the system clocks to powergraphics speed*/
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LOG(2,("INIT: Setting system PLL to powergraphics speeds\n"));
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g400_dac_set_sys_pll();
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/* 'official' RAM initialisation */
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LOG(2,("INIT: RAM init\n"));
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/* disable hardware plane write mask if SDRAM card */
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// if (si->ps.sdram) CFGW(OPTION,(CFGR(OPTION) & 0xffffbfff));
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/* disable plane write mask (needed for SDRAM): actual change needed to get it sent to RAM */
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// ACCW(PLNWT,0x00000000);
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// ACCW(PLNWT,0xffffffff);
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/* program memory control waitstates */
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// ACCW(MCTLWTST,si->ps.mctlwtst_reg);
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/* set memory configuration including:
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* - SDRAM / SGRAM special functions select. */
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// CFGW(OPTION,(CFGR(OPTION)&0xFFFF83FF) | ((si->ps.v3_mem_type & 0x07) << 10));
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// if (!si->ps.sdram) CFGW(OPTION,(CFGR(OPTION) | (0x01 << 14)));
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/* set memory buffer type */
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// CFGW(OPTION2,(CFGR(OPTION2)&0xFFFFCFFF)|((si->ps.v3_option2_reg & 0x03) << 12));
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/* set mode register opcode and streamer flow control */
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// ACCW(MEMRDBK,(ACCR(MEMRDBK)&0x0000FFFF)|(si->ps.memrdbk_reg & 0xffff0000));
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/* set RAM read tap delays */
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// ACCW(MEMRDBK,(ACCR(MEMRDBK)&0xFFFF0000)|(si->ps.memrdbk_reg & 0x0000ffff));
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/* wait 200uS minimum */
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snooze(250);
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/* reset memory (MACCESS is a write only register!) */
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// ACCW(MACCESS, 0x00000000);
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/* perform actual RAM reset */
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// ACCW(MACCESS, 0x00008000);
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snooze(250);
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/* start memory refresh */
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// CFGW(OPTION,(CFGR(OPTION)&0xffe07fff) | (si->ps.option_reg & 0x001f8000));
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/* set memory control waitstate again AFTER the RAM reset */
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// ACCW(MCTLWTST,si->ps.mctlwtst_reg);
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/* end 'official' RAM initialisation. */
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/* Bus parameters: enable retries, use advanced read */
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// CFGW(OPTION,(CFGR(OPTION)|(1<<22)|(0<<29)));
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/*enable writing to crtc registers*/
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// VGAW_I(CRTC,0x11,0);
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/* turn on display one */
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head1_dpms(true, true, true);
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return B_OK;
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/* do powerup needed from pre-inited card state as done by system POST cardBIOS
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* execution or driver coldstart above */
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return nv_general_bios_to_powergraphics();
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}
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/* this routine switches the CRTC/DAC sets to 'connectors', but only for analog
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@ -970,8 +891,6 @@ status_t nv_general_head_select(bool cross)
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* Should work from VGA BIOS POST init state. */
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static status_t nv_general_bios_to_powergraphics()
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{
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LOG(2, ("INIT: Skipping card coldstart!\n"));
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/* let acc engine make power off/power on cycle to start 'fresh' */
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NV_REG32(NV32_PWRUPCTRL) = 0x13110011;
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snooze(1000);
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@ -20,6 +20,8 @@ static void getstrap_arch_nv4(void);
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static void getstrap_arch_nv10_20_30(void);
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static status_t pins2_read(uint8 *rom, uint32 offset, uint8 ram_cfg);
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static status_t pins3_6_read(uint8 *rom, uint32 offset, uint8 ram_cfg);
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static status_t coldstart_card(uint8* rom, uint16 init1, uint16 init2, uint16 init_size);
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static status_t exec_type1_script(uint8* rom, uint16 adress);
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/* Parse the BIOS PINS structure if there */
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status_t parse_pins ()
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@ -85,13 +87,13 @@ status_t parse_pins ()
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switch (rom[offset + 5])
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{
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case 2:
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pins2_read(rom, offset, ram_cfg);
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result = pins2_read(rom, offset, ram_cfg);
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break;
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case 3:
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case 4:
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case 5:
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case 6:
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pins3_6_read(rom, offset, ram_cfg);
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result = pins3_6_read(rom, offset, ram_cfg);
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break;
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default:
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LOG(8,("INFO: unknown PINS version\n"));
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@ -102,7 +104,7 @@ status_t parse_pins ()
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/* check PINS read result */
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if (result == B_ERROR)
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{
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LOG(8,("INFO: PINS read/decode error\n"));
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LOG(8,("INFO: PINS read/decode/execute error\n"));
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return B_ERROR;
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}
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/* PINS scan succeeded */
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@ -127,7 +129,7 @@ static status_t pins2_read(uint8 *rom, uint32 offset, uint8 ram_cfg)
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LOG(8,("INFO: product name: %s\n", product_name));
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LOG(8,("INFO: product rev: %s\n", product_rev));
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return B_ERROR;
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return coldstart_card(rom, init1, init2, init_size);
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}
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static status_t pins3_6_read(uint8 *rom, uint32 offset, uint8 ram_cfg)
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@ -163,92 +165,51 @@ static status_t pins3_6_read(uint8 *rom, uint32 offset, uint8 ram_cfg)
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}
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*/ }
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return B_ERROR;
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return coldstart_card(rom, init1, init2, init_size);
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}
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/* pins v5 is used by G450 and G550 */
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/*
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static status_t pinsx_read(uint8 *pins, uint8 length)
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static status_t coldstart_card(uint8* rom, uint16 init1, uint16 init2, uint16 init_size)
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{
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unsigned int m_factor = 6;
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status_t result = B_OK;
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if (length != 128)
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LOG(8,("INFO: executing coldstart...\n"));
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/* turn off both displays and the hardcursors (also disables transfers) */
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nv_crtc_dpms(false, false, false);
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nv_crtc_cursor_hide();
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if (si->ps.secondary_head)
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{
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LOG(8,("INFO: wrong PINS length, expected 128, got %d\n", length));
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return B_ERROR;
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nv_crtc2_dpms(false, false, false);
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nv_crtc2_cursor_hide();
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}
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// fill out the shared info si->ps struct
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if (pins[4] == 0x01) m_factor = 8;
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if (pins[4] >= 0x02) m_factor = 10;
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si->ps.max_system_vco = m_factor * pins[36];
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si->ps.max_video_vco = m_factor * pins[37];
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si->ps.max_pixel_vco = m_factor * pins[38];
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si->ps.min_system_vco = m_factor * pins[121];
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si->ps.min_video_vco = m_factor * pins[122];
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si->ps.min_pixel_vco = m_factor * pins[123];
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if (pins[39] == 0xff) si->ps.max_dac1_clock_8 = si->ps.max_pixel_vco;
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else si->ps.max_dac1_clock_8 = 4 * pins[39];
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if (pins[40] == 0xff) si->ps.max_dac1_clock_16 = si->ps.max_dac1_clock_8;
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else si->ps.max_dac1_clock_16 = 4 * pins[40];
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if (pins[41] == 0xff) si->ps.max_dac1_clock_24 = si->ps.max_dac1_clock_16;
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else si->ps.max_dac1_clock_24 = 4 * pins[41];
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if (pins[42] == 0xff) si->ps.max_dac1_clock_32 = si->ps.max_dac1_clock_24;
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else si->ps.max_dac1_clock_32 = 4 * pins[42];
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if (pins[124] == 0xff) si->ps.max_dac1_clock_32dh = si->ps.max_dac1_clock_32;
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else si->ps.max_dac1_clock_32dh = 4 * pins[124];
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if (pins[43] == 0xff) si->ps.max_dac2_clock_16 = si->ps.max_video_vco;
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else si->ps.max_dac2_clock_16 = 4 * pins[43];
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if (pins[44] == 0xff) si->ps.max_dac2_clock_32 = si->ps.max_dac2_clock_16;
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else si->ps.max_dac2_clock_32 = 4 * pins[44];
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if (pins[125] == 0xff) si->ps.max_dac2_clock_32dh = si->ps.max_dac2_clock_32;
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else si->ps.max_dac2_clock_32dh = 4 * pins[125];
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if (pins[118] == 0xff) si->ps.max_dac1_clock = si->ps.max_dac1_clock_8;
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else si->ps.max_dac1_clock = 4 * pins[118];
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if (pins[119] == 0xff) si->ps.max_dac2_clock = si->ps.max_dac1_clock;
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else si->ps.max_dac2_clock = 4 * pins[119];
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si->ps.std_engine_clock = 4 * pins[74];
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si->ps.std_memory_clock = 4 * pins[92];
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si->ps.memory_size = ((pins[114] & 0x03) + 1) * 8;
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if ((pins[114] & 0x07) > 3)
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/* execute BIOS coldstart script(s) */
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if (init1 || init2)
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{
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LOG(8,("INFO: unknown RAM size, defaulting to 8Mb\n"));
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si->ps.memory_size = 8;
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if (init1)
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if (exec_type1_script(rom, init1) != B_OK) result = B_ERROR;
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if (init2)
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if (exec_type1_script(rom, init2) != B_OK) result = B_ERROR;
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}
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else
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{
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result = B_ERROR;
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}
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if (pins[110] & 0x01) si->ps.f_ref = 14.31818;
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else si->ps.f_ref = 27.00000;
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if (result != B_OK)
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LOG(8,("INFO: coldstart failed.\n"));
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else
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LOG(8,("INFO: coldstart execution completed OK.\n"));
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// make sure SGRAM functions only get enabled if SGRAM mounted
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// if ((pins[114] & 0x18) == 0x08) si->ps.sdram = false;
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// else si->ps.sdram = true;
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return result;
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}
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// various registers
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si->ps.secondary_head = (pins[117] & 0x70);
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si->ps.tvout = (pins[117] & 0x40);
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si->ps.primary_dvi = (pins[117] & 0x02);
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si->ps.secondary_dvi = (pins[117] & 0x20);
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// not supported:
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si->ps.max_dac2_clock_8 = 0;
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si->ps.max_dac2_clock_24 = 0;
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static status_t exec_type1_script(uint8* rom, uint16 adress)
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{
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//fixme...
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return B_OK;
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}
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*/
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/* fake_pins presumes the card was coldstarted by it's BIOS */
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void fake_pins(void)
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@ -89,6 +89,20 @@ Please read this information carefully *before* installing and using the (open)B
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<br>
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<strong>nv.settings driver configuration:</strong><br>
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<ul>
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<li><strong>usebios:</strong><br>
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The name of this item may be somewhat misleading, it might be changed in the future. It actually tells the driver if it should coldstart the card or not. The driver will rely on the VGA BIOS to have coldstarted the card before BeOS booted if you specify 'true'.<br>
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To make things look even more complex the driver might actually use the BIOS to determine your cards specifications on *both* possible settings.
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<ul>
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<li><strong>false:</strong><br>
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If you specify <strong>usebios false</strong> the driver will attempt to coldstart the card, which is the preferred way of doing it because of the better tuned setup if all is right. Unfortunately there's not enough info available to make this work reliably, so it's not used by default. This setting would enable you to use your nVidia card as a secondary card in your system. Be advised though that BeOS officially does not (yet) support multiple VGA cards, so you need special software in order to be able to actually use it (a video consumer node for instance).
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<li><strong>true:</strong> (default setting)<br>
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Specify <strong>usebios true</strong> unless you want to try to use a nVidia card as a secondary card in your system.
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</ul>
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<strong>Notes:</strong>
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<ul>
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<li>On driverversion 0.23 and before usebios had no effect at all. The cards were never coldstarted.
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<li>Coldstarting is more likely to succeed on TNT and older GeForce cards than it is on newer cards.
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</ul>
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<li><strong>memory:</strong> (disabled by default)<br>
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This option enables you to override the 'memory amount autodetection' of the driver. If autodetection is working incorrect, you can manually set the amount this way. You could also lower the amount of RAM to a lower value than actually there to test with for instance overlay use in applications. So this option is probably mostly of interest to developers. Specify the RAM amount in Mb (use only 'whole' numbers!).<br>
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This option is disabled by default (preceded by a '#').<br>
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@ -159,6 +173,6 @@ With the <strong>pgm_panel true</strong> setting, the driver will fix your panel
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<hr>
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<br>
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<a href="mailto:info.be-hold@inter.nl.net">Rudolf Cornelissen.</a>
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<p>(Page last updated on July 19, 2004)</p>
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<p>(Page last updated on August 26, 2004)</p>
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</body>
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</html>
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@ -4,9 +4,10 @@
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</head>
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<body>
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<p><h2>Changes done for each driverversion:</h2></p>
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<p><h1>head 0.23, (Rudolf)</h1></p>
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<p><h1>head 0.24, (Rudolf)</h1></p>
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<ul>
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<li>Overlay fix for GeForce2 and GeForce4 MX Integrated GPU boards: updated RAM amount detection. The last 64Kb RAM is used for the card's BIOS or something so it's not available to the graphicsdriver.
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<li>Overlay fix for GeForce2 and GeForce4 MX Integrated GPU boards: updated RAM amount detection. The last 64Kb RAM is used for the card's BIOS or something so it's not available to the graphicsdriver;
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<li>Enabled coldstart switch setting (called 'usebios' in nv.settings) in drivercode. Changed the setting to keep the driver working as always; if you modify it a card coldstart might be attempted (in progress).
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</ul>
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<p><h1>nv_driver 0.22, (Rudolf)</h1></p>
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<ul>
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@ -8,7 +8,7 @@
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# accelerant "nv.accelerant"
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# nv.accelerant parameters
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usebios false # if true rely on bios to coldstart the card: not working, so always true
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usebios true # if true rely on bios to coldstart the card
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#memory 2 # in MB, override builtin memory size detection
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hardcursor true # if true use on-chip cursor capabilities
|
||||
#logmask 0x00000000 # nothing logged, is default
|
||||
|
||||
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Reference in New Issue
Block a user