diff --git a/src/add-ons/accelerants/nvidia/engine/nv_general.c b/src/add-ons/accelerants/nvidia/engine/nv_general.c index 41e4d0a408..ff5b7767b6 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_general.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_general.c @@ -1,7 +1,7 @@ /* Authors: Mark Watson 12/1999, Apsed, - Rudolf Cornelissen 10/2002-7/2004 + Rudolf Cornelissen 10/2002-8/2004 */ #define MODULE_BIT 0x00008000 @@ -80,7 +80,7 @@ status_t nv_general_powerup() { status_t status; - LOG(1,("POWERUP: nVidia (open)BeOS Accelerant 0.23 running.\n")); + LOG(1,("POWERUP: nVidia (open)BeOS Accelerant 0.24 running.\n")); /* preset no laptop */ si->ps.laptop = false; @@ -781,115 +781,36 @@ void set_crtc_owner(bool head) static status_t nvxx_general_powerup() { - status_t result; - LOG(4, ("INIT: NV powerup\n")); if (si->settings.logmask & 0x80000000) nv_dump_configuration_space(); - /* initialize the shared_info PINS struct */ - result = parse_pins(); -// if (result != B_OK) fake_pins(); -//temporary: + /* fill-in the cardspecs in the shared_info PINS struct */ fake_pins(); - - /* log the PINS struct settings */ + /* only process BIOS for specs and coldstart if requested by user; + * note: + * this in fact frees the driver from relying on the BIOS to be executed + * at system power-up POST time. */ + if (!si->settings.usebios) + { + LOG(2, ("INIT: Attempting card coldstart!\n")); + /* update the cardspecs in the shared_info PINS struct according to reported + * specs as much as is possible; + * this also coldstarts the card if possible (executes BIOS CMD script(s)) */ + parse_pins(); + } + else + { + LOG(2, ("INIT: Skipping card coldstart!\n")); + } + /* log the final PINS struct settings */ dump_pins(); - /* setup CRTC and DAC functions access: determined in parse_pins/fake_pins */ + /* setup CRTC and DAC functions access: determined in fake_pins */ setup_virtualized_heads(si->ps.crtc2_prim); - /* if the user doesn't want a coldstart OR the BIOS pins info could not be found warmstart */ -//temp: -return nv_general_bios_to_powergraphics(); - if (si->settings.usebios || (result != B_OK)) return nv_general_bios_to_powergraphics(); - - /*power up the PLLs,LUT,DAC*/ - LOG(2,("INIT: PLL/LUT/DAC powerup\n")); - - /* turn off both displays and the hardcursors (also disables transfers) */ - head1_dpms(false, false, false); - head1_cursor_hide(); - if (si->ps.secondary_head) - { - head2_dpms(false, false, false); - head2_cursor_hide(); - } - - /* G200 SGRAM and SDRAM use external pix and dac refs, do *not* activate internals! - * (this would create electrical shortcuts, - * resulting in extra chip heat and distortions visible on screen */ - /* set voltage reference - using DAC reference block partly */ -// DXIW(VREFCTRL,0x03); - /* wait for 100ms for voltage reference to stabilize */ - delay(100000); - /* power up the SYSPLL */ -// CFGW(OPTION,CFGR(OPTION)|0x20); - /* power up the PIXPLL */ -// DXIW(PIXCLKCTRL,0x08); - - /* disable pixelclock oscillations before switching on CLUT */ -// DXIW(PIXCLKCTRL, (DXIR(PIXCLKCTRL) | 0x04)); - /* disable 15bit mode CLUT-overlay function */ -// DXIW(GENCTRL, DXIR(GENCTRL & 0xfd)); - /* CRTC2->MAFC, 8-bit DAC, CLUT enabled, enable DAC */ -// DXIW(MISCCTRL,0x1b); - snooze(250); - /* re-enable pixelclock oscillations */ -// DXIW(PIXCLKCTRL, (DXIR(PIXCLKCTRL) & 0xfb)); - - /* setup i2c bus */ - i2c_init(); - - /*make sure card is in powergraphics mode*/ -// VGAW_I(CRTCEXT,3,0x80); - - /*set the system clocks to powergraphics speed*/ - LOG(2,("INIT: Setting system PLL to powergraphics speeds\n")); - g400_dac_set_sys_pll(); - - /* 'official' RAM initialisation */ - LOG(2,("INIT: RAM init\n")); - /* disable hardware plane write mask if SDRAM card */ -// if (si->ps.sdram) CFGW(OPTION,(CFGR(OPTION) & 0xffffbfff)); - /* disable plane write mask (needed for SDRAM): actual change needed to get it sent to RAM */ -// ACCW(PLNWT,0x00000000); -// ACCW(PLNWT,0xffffffff); - /* program memory control waitstates */ -// ACCW(MCTLWTST,si->ps.mctlwtst_reg); - /* set memory configuration including: - * - SDRAM / SGRAM special functions select. */ -// CFGW(OPTION,(CFGR(OPTION)&0xFFFF83FF) | ((si->ps.v3_mem_type & 0x07) << 10)); -// if (!si->ps.sdram) CFGW(OPTION,(CFGR(OPTION) | (0x01 << 14))); - /* set memory buffer type */ -// CFGW(OPTION2,(CFGR(OPTION2)&0xFFFFCFFF)|((si->ps.v3_option2_reg & 0x03) << 12)); - /* set mode register opcode and streamer flow control */ -// ACCW(MEMRDBK,(ACCR(MEMRDBK)&0x0000FFFF)|(si->ps.memrdbk_reg & 0xffff0000)); - /* set RAM read tap delays */ -// ACCW(MEMRDBK,(ACCR(MEMRDBK)&0xFFFF0000)|(si->ps.memrdbk_reg & 0x0000ffff)); - /* wait 200uS minimum */ - snooze(250); - - /* reset memory (MACCESS is a write only register!) */ -// ACCW(MACCESS, 0x00000000); - /* perform actual RAM reset */ -// ACCW(MACCESS, 0x00008000); - snooze(250); - /* start memory refresh */ -// CFGW(OPTION,(CFGR(OPTION)&0xffe07fff) | (si->ps.option_reg & 0x001f8000)); - /* set memory control waitstate again AFTER the RAM reset */ -// ACCW(MCTLWTST,si->ps.mctlwtst_reg); - /* end 'official' RAM initialisation. */ - - /* Bus parameters: enable retries, use advanced read */ -// CFGW(OPTION,(CFGR(OPTION)|(1<<22)|(0<<29))); - - /*enable writing to crtc registers*/ -// VGAW_I(CRTC,0x11,0); - - /* turn on display one */ - head1_dpms(true, true, true); - - return B_OK; + /* do powerup needed from pre-inited card state as done by system POST cardBIOS + * execution or driver coldstart above */ + return nv_general_bios_to_powergraphics(); } /* this routine switches the CRTC/DAC sets to 'connectors', but only for analog @@ -970,8 +891,6 @@ status_t nv_general_head_select(bool cross) * Should work from VGA BIOS POST init state. */ static status_t nv_general_bios_to_powergraphics() { - LOG(2, ("INIT: Skipping card coldstart!\n")); - /* let acc engine make power off/power on cycle to start 'fresh' */ NV_REG32(NV32_PWRUPCTRL) = 0x13110011; snooze(1000); diff --git a/src/add-ons/accelerants/nvidia/engine/nv_info.c b/src/add-ons/accelerants/nvidia/engine/nv_info.c index 4019510e8c..3195073d16 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_info.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_info.c @@ -20,6 +20,8 @@ static void getstrap_arch_nv4(void); static void getstrap_arch_nv10_20_30(void); static status_t pins2_read(uint8 *rom, uint32 offset, uint8 ram_cfg); static status_t pins3_6_read(uint8 *rom, uint32 offset, uint8 ram_cfg); +static status_t coldstart_card(uint8* rom, uint16 init1, uint16 init2, uint16 init_size); +static status_t exec_type1_script(uint8* rom, uint16 adress); /* Parse the BIOS PINS structure if there */ status_t parse_pins () @@ -85,13 +87,13 @@ status_t parse_pins () switch (rom[offset + 5]) { case 2: - pins2_read(rom, offset, ram_cfg); + result = pins2_read(rom, offset, ram_cfg); break; case 3: case 4: case 5: case 6: - pins3_6_read(rom, offset, ram_cfg); + result = pins3_6_read(rom, offset, ram_cfg); break; default: LOG(8,("INFO: unknown PINS version\n")); @@ -102,7 +104,7 @@ status_t parse_pins () /* check PINS read result */ if (result == B_ERROR) { - LOG(8,("INFO: PINS read/decode error\n")); + LOG(8,("INFO: PINS read/decode/execute error\n")); return B_ERROR; } /* PINS scan succeeded */ @@ -127,7 +129,7 @@ static status_t pins2_read(uint8 *rom, uint32 offset, uint8 ram_cfg) LOG(8,("INFO: product name: %s\n", product_name)); LOG(8,("INFO: product rev: %s\n", product_rev)); - return B_ERROR; + return coldstart_card(rom, init1, init2, init_size); } static status_t pins3_6_read(uint8 *rom, uint32 offset, uint8 ram_cfg) @@ -163,92 +165,51 @@ static status_t pins3_6_read(uint8 *rom, uint32 offset, uint8 ram_cfg) } */ } - return B_ERROR; + return coldstart_card(rom, init1, init2, init_size); } -/* pins v5 is used by G450 and G550 */ -/* -static status_t pinsx_read(uint8 *pins, uint8 length) +static status_t coldstart_card(uint8* rom, uint16 init1, uint16 init2, uint16 init_size) { - unsigned int m_factor = 6; + status_t result = B_OK; - if (length != 128) + LOG(8,("INFO: executing coldstart...\n")); + + /* turn off both displays and the hardcursors (also disables transfers) */ + nv_crtc_dpms(false, false, false); + nv_crtc_cursor_hide(); + if (si->ps.secondary_head) { - LOG(8,("INFO: wrong PINS length, expected 128, got %d\n", length)); - return B_ERROR; + nv_crtc2_dpms(false, false, false); + nv_crtc2_cursor_hide(); } - // fill out the shared info si->ps struct - if (pins[4] == 0x01) m_factor = 8; - if (pins[4] >= 0x02) m_factor = 10; - - si->ps.max_system_vco = m_factor * pins[36]; - si->ps.max_video_vco = m_factor * pins[37]; - si->ps.max_pixel_vco = m_factor * pins[38]; - si->ps.min_system_vco = m_factor * pins[121]; - si->ps.min_video_vco = m_factor * pins[122]; - si->ps.min_pixel_vco = m_factor * pins[123]; - - if (pins[39] == 0xff) si->ps.max_dac1_clock_8 = si->ps.max_pixel_vco; - else si->ps.max_dac1_clock_8 = 4 * pins[39]; - - if (pins[40] == 0xff) si->ps.max_dac1_clock_16 = si->ps.max_dac1_clock_8; - else si->ps.max_dac1_clock_16 = 4 * pins[40]; - - if (pins[41] == 0xff) si->ps.max_dac1_clock_24 = si->ps.max_dac1_clock_16; - else si->ps.max_dac1_clock_24 = 4 * pins[41]; - - if (pins[42] == 0xff) si->ps.max_dac1_clock_32 = si->ps.max_dac1_clock_24; - else si->ps.max_dac1_clock_32 = 4 * pins[42]; - - if (pins[124] == 0xff) si->ps.max_dac1_clock_32dh = si->ps.max_dac1_clock_32; - else si->ps.max_dac1_clock_32dh = 4 * pins[124]; - - if (pins[43] == 0xff) si->ps.max_dac2_clock_16 = si->ps.max_video_vco; - else si->ps.max_dac2_clock_16 = 4 * pins[43]; - - if (pins[44] == 0xff) si->ps.max_dac2_clock_32 = si->ps.max_dac2_clock_16; - else si->ps.max_dac2_clock_32 = 4 * pins[44]; - - if (pins[125] == 0xff) si->ps.max_dac2_clock_32dh = si->ps.max_dac2_clock_32; - else si->ps.max_dac2_clock_32dh = 4 * pins[125]; - - if (pins[118] == 0xff) si->ps.max_dac1_clock = si->ps.max_dac1_clock_8; - else si->ps.max_dac1_clock = 4 * pins[118]; - - if (pins[119] == 0xff) si->ps.max_dac2_clock = si->ps.max_dac1_clock; - else si->ps.max_dac2_clock = 4 * pins[119]; - - si->ps.std_engine_clock = 4 * pins[74]; - si->ps.std_memory_clock = 4 * pins[92]; - - si->ps.memory_size = ((pins[114] & 0x03) + 1) * 8; - if ((pins[114] & 0x07) > 3) + /* execute BIOS coldstart script(s) */ + if (init1 || init2) { - LOG(8,("INFO: unknown RAM size, defaulting to 8Mb\n")); - si->ps.memory_size = 8; + if (init1) + if (exec_type1_script(rom, init1) != B_OK) result = B_ERROR; + if (init2) + if (exec_type1_script(rom, init2) != B_OK) result = B_ERROR; + } + else + { + result = B_ERROR; } - if (pins[110] & 0x01) si->ps.f_ref = 14.31818; - else si->ps.f_ref = 27.00000; + if (result != B_OK) + LOG(8,("INFO: coldstart failed.\n")); + else + LOG(8,("INFO: coldstart execution completed OK.\n")); - // make sure SGRAM functions only get enabled if SGRAM mounted -// if ((pins[114] & 0x18) == 0x08) si->ps.sdram = false; -// else si->ps.sdram = true; + return result; +} - // various registers - si->ps.secondary_head = (pins[117] & 0x70); - si->ps.tvout = (pins[117] & 0x40); - si->ps.primary_dvi = (pins[117] & 0x02); - si->ps.secondary_dvi = (pins[117] & 0x20); - - // not supported: - si->ps.max_dac2_clock_8 = 0; - si->ps.max_dac2_clock_24 = 0; +static status_t exec_type1_script(uint8* rom, uint16 adress) +{ + //fixme... return B_OK; } -*/ /* fake_pins presumes the card was coldstarted by it's BIOS */ void fake_pins(void) diff --git a/src/add-ons/kernel/drivers/graphics/nvidia/README.html b/src/add-ons/kernel/drivers/graphics/nvidia/README.html index c11bf90756..46d1473d4c 100644 --- a/src/add-ons/kernel/drivers/graphics/nvidia/README.html +++ b/src/add-ons/kernel/drivers/graphics/nvidia/README.html @@ -89,6 +89,20 @@ Please read this information carefully *before* installing and using the (open)B
nv.settings driver configuration: