added 2D_surface setup (DMA), added fifo channel assignent check for aquire_engine, cleaned some stuff up.
git-svn-id: file:///srv/svn/repos/haiku/trunk/current@10793 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
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a9b9a9147e
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02e231b77b
@ -4,7 +4,7 @@
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other authors:
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Mark Watson
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Rudolf Cornelissen 3/2004-12/2004
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Rudolf Cornelissen 3/2004-1/2005
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*/
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/*
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@ -37,6 +37,8 @@ status_t ACQUIRE_ENGINE(uint32 capabilities, uint32 max_wait, sync_token *st, en
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/* make sure all needed engine cmd's are mapped to the FIFO */
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if (si->ps.card_arch < NV40A)
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nv_acc_assert_fifo();
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else
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nv_acc_assert_fifo_dma();
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/* return an engine token */
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*et = &nv_engine_token;
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@ -651,7 +651,8 @@ status_t nv_acc_init()
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}
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ACCW(PR_CTX1_D, 0x00000c02); /* format is X16RGB16, LSB mono */
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break;
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case B_RGB32_LITTLE:case B_RGBA32_LITTLE:
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case B_RGB32_LITTLE:
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case B_RGBA32_LITTLE:
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/* acc engine */
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ACCW(FORMATS, 0x000070e5);
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if (si->ps.card_arch < NV30A)
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@ -30,7 +30,7 @@ blit
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static void nv_start_dma(void);
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static status_t nv_acc_fifofree_dma(uint16 cmd_size);
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static void nv_acc_assert_fifo_dma(void);
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static void nv_acc_cmd_dma(uint32 cmd, uint16 offset, uint16 size);
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status_t nv_acc_wait_idle_dma()
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{
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@ -60,6 +60,7 @@ status_t nv_acc_wait_idle_dma()
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status_t nv_acc_init_dma()
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{
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uint16 cnt;
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uint32 depth;
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//fixme: move to shared info:
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uint32 max;
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@ -557,8 +558,8 @@ status_t nv_acc_init_dma()
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/* enable PFIFO caches reassign */
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ACCW(PF_CACHES, 0x00000001);
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/*** setup acceleration engine command shortcuts (so via fifo) ***/
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/* set object handles (b31 = 1 selects 'config' function?) */
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/*** init acceleration engine command info ***/
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/* set object handles */
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/* note:
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* probably depending on some other setup, there are 8 or 32 FIFO channels
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* available. Assuming the current setup only has 8 channels because the 'rest'
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@ -585,70 +586,15 @@ status_t nv_acc_init_dma()
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(0x00000001 + (cnt * 0x00002000));
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}
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/* init DMA command buffer pointer */
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/*** init DMA command buffer info ***/
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si->engine.dma.cmdbuffer = (uint32 *)((char *)si->framebuffer +
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((si->ps.memory_size - 1) & 0xffff8000));
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LOG(4,("ACC_DMA: command buffer is at adress $%08x\n",
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((uint32)(si->engine.dma.cmdbuffer))));
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/* init FIFO via DMA command buffer. */
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/* NV_FIFO_DMA_OPCODE: set number of cmd words (b18 - 28); set FIFO offset for
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* first cmd word (b2 - 15); set DMA opcode = method (b29 - 31).
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* a 'NOP' is the opcode word $00000000. */
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/* note:
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* possible DMA opcodes:
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* b'000' is 'method' (execute cmd);
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* b'001' is 'jump';
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* b'002' is 'noninc method' (execute buffer wrap-around);
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* b'003' is 'call': return is executed by opcode word $00020000 (b17 = 1). */
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/* note also:
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* this system uses auto-increments for the FIFO offset adresses. Make sure
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* to set new adresses if jumps are needed. */
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si->engine.dma.cmdbuffer[0x00] = (1 << 18) | 0x00000;
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/* send actual cmd word */
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si->engine.dma.cmdbuffer[0x01] =
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(0x80000000 | si->engine.fifo.handle[0]); /* Raster OPeration */
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/* etc.. */
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si->engine.dma.cmdbuffer[0x02] = (1 << 18) | 0x02000;
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si->engine.dma.cmdbuffer[0x03] =
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(0x80000000 | si->engine.fifo.handle[1]); /* Clip */
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si->engine.dma.cmdbuffer[0x04] = (1 << 18) | 0x04000;
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si->engine.dma.cmdbuffer[0x05] =
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(0x80000000 | si->engine.fifo.handle[2]); /* Pattern */
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si->engine.dma.cmdbuffer[0x06] = (1 << 18) | 0x06000;
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si->engine.dma.cmdbuffer[0x07] =
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(0x80000000 | si->engine.fifo.handle[3]); /* 2D Surface */
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si->engine.dma.cmdbuffer[0x08] = (1 << 18) | 0x08000;
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si->engine.dma.cmdbuffer[0x09] =
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(0x80000000 | si->engine.fifo.handle[4]); /* Blit */
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si->engine.dma.cmdbuffer[0x0a] = (1 << 18) | 0x0a000;
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si->engine.dma.cmdbuffer[0x0b] =
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(0x80000000 | si->engine.fifo.handle[5]); /* Bitmap */
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si->engine.dma.cmdbuffer[0x0c] = (1 << 18) | 0x0c000;
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// si->engine.dma.cmdbuffer[0x0d] =
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// (0x80000000 | si->engine.fifo.handle[6]); /* Line (not used or 3D only?) */
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//fixme: temporary so there's something valid here.. (maybe needed, don't yet know)
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si->engine.dma.cmdbuffer[0x0d] =
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(0x80000000 | si->engine.fifo.handle[0]);
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si->engine.dma.cmdbuffer[0x0e] = (1 << 18) | 0x0e000;
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// si->engine.dma.cmdbuffer[0x0f] =
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// (0x80000000 | si->engine.fifo.handle[7]); /* Textured Triangle (3D only) */
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//fixme: temporary so there's something valid here.. (maybe needed, don't yet know)
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si->engine.dma.cmdbuffer[0x0f] =
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(0x80000000 | si->engine.fifo.handle[0]);
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/* we have issued no DMA cmd's to the engine yet: the above ones are still
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* awaiting execution start. */
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/* we have issued no DMA cmd's to the engine yet */
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si->engine.dma.put = 0;
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/* the current first free adress in the DMA buffer is at offset 16 */
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si->engine.dma.current = 16;
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/* the current first free adress in the DMA buffer is at offset 0 */
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si->engine.dma.current = 0;
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/* the DMA buffer can hold 8k 32-bit words (it's 32kb in size) */
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/* note:
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* one word is reserved at the end of the DMA buffer to be able to instruct the
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@ -658,15 +604,79 @@ status_t nv_acc_init_dma()
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/* note the current free space we have left in the DMA buffer */
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si->engine.dma.free = /*si->dma.*/max - si->engine.dma.current /*+ 1*/;
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/* initialize our local pointers */
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nv_acc_assert_fifo_dma();
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/*** init FIFO via DMA command buffer. ***/
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nv_acc_cmd_dma(NV_GENERAL_FIFO_CH0, NV_GENERAL_CMDHANDLE, 1);
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si->engine.dma.cmdbuffer[si->engine.dma.current++] =
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(0x80000000 | si->engine.fifo.handle[0]); /* Raster OPeration */
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nv_acc_cmd_dma(NV_GENERAL_FIFO_CH1, NV_GENERAL_CMDHANDLE, 1);
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si->engine.dma.cmdbuffer[si->engine.dma.current++] =
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(0x80000000 | si->engine.fifo.handle[1]); /* Clip */
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nv_acc_cmd_dma(NV_GENERAL_FIFO_CH2, NV_GENERAL_CMDHANDLE, 1);
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si->engine.dma.cmdbuffer[si->engine.dma.current++] =
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(0x80000000 | si->engine.fifo.handle[2]); /* Pattern */
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nv_acc_cmd_dma(NV_GENERAL_FIFO_CH3, NV_GENERAL_CMDHANDLE, 1);
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si->engine.dma.cmdbuffer[si->engine.dma.current++] =
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(0x80000000 | si->engine.fifo.handle[3]); /* 2D Surface */
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nv_acc_cmd_dma(NV_GENERAL_FIFO_CH4, NV_GENERAL_CMDHANDLE, 1);
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si->engine.dma.cmdbuffer[si->engine.dma.current++] =
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(0x80000000 | si->engine.fifo.handle[4]); /* Blit */
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nv_acc_cmd_dma(NV_GENERAL_FIFO_CH5, NV_GENERAL_CMDHANDLE, 1);
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si->engine.dma.cmdbuffer[si->engine.dma.current++] =
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(0x80000000 | si->engine.fifo.handle[5]); /* Bitmap */
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nv_acc_cmd_dma(NV_GENERAL_FIFO_CH6, NV_GENERAL_CMDHANDLE, 1);
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si->engine.dma.cmdbuffer[si->engine.dma.current++] =
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//fixme: temporary so there's something valid here.. (maybe needed, don't yet know)
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// (0x80000000 | si->engine.fifo.handle[6]); /* Line (not used or 3D only?) */
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(0x80000000 | si->engine.fifo.handle[0]);
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nv_acc_cmd_dma(NV_GENERAL_FIFO_CH7, NV_GENERAL_CMDHANDLE, 1);
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si->engine.dma.cmdbuffer[si->engine.dma.current++] =
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//fixme: temporary so there's something valid here.. (maybe needed, don't yet know)
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// (0x80000000 | si->engine.fifo.handle[7]); /* Textured Triangle (3D only) */
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(0x80000000 | si->engine.fifo.handle[0]);
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//fixme: add colorspace and buffer config cmd's or predefine in the non-DMA way.
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//fixme: overlay should stay outside the DMA buffer, also add a failsafe
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// space in between both functions as errors might hang the engine!
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/*** Set pixel width ***/
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switch(si->dm.space)
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{
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case B_CMAP8:
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depth = 0x00000001;
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break;
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case B_RGB15_LITTLE:
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depth = 0x00000004;
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break;
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case B_RGB16_LITTLE:
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depth = 0x00000004;
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break;
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case B_RGB32_LITTLE:
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case B_RGBA32_LITTLE:
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depth = 0x00000006;
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break;
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default:
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LOG(8,("ACC: init, invalid bit depth\n"));
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return B_ERROR;
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}
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/* tell the engine to fetch the commands in the DMA buffer that where not
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* executed before. */
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/* now setup 2D surface (writing 5 32bit words) */
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nv_acc_cmd_dma(NV4_SURFACE, NV4_SURFACE_FORMAT, 4);
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si->engine.dma.cmdbuffer[si->engine.dma.current++] = depth; /* Format */
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/* setup screen pitch */
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si->engine.dma.cmdbuffer[si->engine.dma.current++] =
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((si->fbc.bytes_per_row & 0x0000ffff) | (si->fbc.bytes_per_row << 16)); /* Pitch */
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/* setup screen location */
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si->engine.dma.cmdbuffer[si->engine.dma.current++] =
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((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer); /* OffsetSource */
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si->engine.dma.cmdbuffer[si->engine.dma.current++] =
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((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer); /* OffsetDest */
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/* tell the engine to fetch and execute all (new) commands in the DMA buffer */
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nv_start_dma();
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return B_OK;
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@ -716,8 +726,20 @@ static status_t nv_acc_fifofree_dma(uint16 cmd_size)
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static void nv_acc_cmd_dma(uint32 cmd, uint16 offset, uint16 size)
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{
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/* NV_FIFO_DMA_OPCODE: set number of cmd words (b18 - 28); set FIFO offset for
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* first cmd word (b2 - 15); set DMA opcode = method (b29 - 31).
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* a 'NOP' is the opcode word $00000000. */
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/* note:
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* possible DMA opcodes:
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* b'000' is 'method' (execute cmd);
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* b'001' is 'jump';
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* b'002' is 'noninc method' (execute buffer wrap-around);
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* b'003' is 'call': return is executed by opcode word $00020000 (b17 = 1). */
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/* note also:
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* this system uses auto-increments for the FIFO offset adresses. Make sure
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* to set a new adress if a gap exists between the previous one and the new one. */
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si->engine.dma.cmdbuffer[si->engine.dma.current++] = ((size << 18) |
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((si->engine.fifo.ch_ptr[cmd] & 0x0000fffc) + offset));
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((si->engine.fifo.ch_ptr[cmd] + offset) & 0x0000fffc));
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}
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/* fixme? (check this out..)
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@ -727,7 +749,7 @@ static void nv_acc_cmd_dma(uint32 cmd, uint16 offset, uint16 size)
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* well be that the assignment is buffered along with the commands that still have to
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* be executed!
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* (sounds very plausible to me :) */
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static void nv_acc_assert_fifo_dma(void)
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void nv_acc_assert_fifo_dma(void)
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{
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/* does every engine cmd this accelerant needs have a FIFO channel? */
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//fixme: can probably be optimized for both speed and channel selection...
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@ -769,13 +791,32 @@ static void nv_acc_assert_fifo_dma(void)
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}
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/* program new FIFO assignments */
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//fixme: should be done via DMA cmd buffer...
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//ACCW(FIFO_CH0, (0x80000000 | si->engine.fifo.handle[0])); /* Raster OPeration */
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//ACCW(FIFO_CH1, (0x80000000 | si->engine.fifo.handle[1])); /* Clip */
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//ACCW(FIFO_CH2, (0x80000000 | si->engine.fifo.handle[2])); /* Pattern */
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//ACCW(FIFO_CH3, (0x80000000 | si->engine.fifo.handle[3])); /* 2D Surface */
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//ACCW(FIFO_CH4, (0x80000000 | si->engine.fifo.handle[4])); /* Blit */
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//ACCW(FIFO_CH5, (0x80000000 | si->engine.fifo.handle[5])); /* Bitmap */
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nv_acc_cmd_dma(NV_GENERAL_FIFO_CH0, NV_GENERAL_CMDHANDLE, 1);
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si->engine.dma.cmdbuffer[si->engine.dma.current++] =
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(0x80000000 | si->engine.fifo.handle[0]); /* Raster OPeration */
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nv_acc_cmd_dma(NV_GENERAL_FIFO_CH1, NV_GENERAL_CMDHANDLE, 1);
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si->engine.dma.cmdbuffer[si->engine.dma.current++] =
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(0x80000000 | si->engine.fifo.handle[1]); /* Clip */
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nv_acc_cmd_dma(NV_GENERAL_FIFO_CH2, NV_GENERAL_CMDHANDLE, 1);
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si->engine.dma.cmdbuffer[si->engine.dma.current++] =
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(0x80000000 | si->engine.fifo.handle[2]); /* Pattern */
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nv_acc_cmd_dma(NV_GENERAL_FIFO_CH3, NV_GENERAL_CMDHANDLE, 1);
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si->engine.dma.cmdbuffer[si->engine.dma.current++] =
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(0x80000000 | si->engine.fifo.handle[3]); /* 2D Surface */
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nv_acc_cmd_dma(NV_GENERAL_FIFO_CH4, NV_GENERAL_CMDHANDLE, 1);
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si->engine.dma.cmdbuffer[si->engine.dma.current++] =
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(0x80000000 | si->engine.fifo.handle[4]); /* Blit */
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nv_acc_cmd_dma(NV_GENERAL_FIFO_CH5, NV_GENERAL_CMDHANDLE, 1);
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si->engine.dma.cmdbuffer[si->engine.dma.current++] =
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(0x80000000 | si->engine.fifo.handle[5]); /* Bitmap */
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/* tell the engine to fetch and execute all (new) commands in the DMA buffer */
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nv_start_dma();
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}
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}
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@ -115,6 +115,7 @@ status_t nv_acc_video_blit(uint16 xs,uint16 ys,uint16 ws, uint16 hs,
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status_t nv_acc_wait_idle(void);
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/* DMA versions */
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status_t nv_acc_init_dma(void);
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void nv_acc_assert_fifo_dma(void);
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status_t nv_acc_setup_blit_dma(void);
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status_t nv_acc_blit_dma(uint16,uint16,uint16, uint16,uint16,uint16 );
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status_t nv_acc_setup_rectangle_dma(uint32 color);
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