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fixed FIFO channel pointer error that caused assert_fifo to always fail (DMA, >NV40). Should fix driver hanging after changing workspaces with different modesettings on NV40 and later.

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git-svn-id: file:///srv/svn/repos/haiku/trunk/current@10792 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen 2005-01-17 10:55:37 +00:00
parent 098ad0a57f
commit a9b9a9147e
1 changed files with 13 additions and 6 deletions
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19
src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c
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@ -577,8 +577,13 @@ status_t nv_acc_init_dma()
si->engine.fifo.ch_ptr[cnt] = 0;
}
/* set handle's pointers to their assigned FIFO channels */
/* note:
* b0-1 aren't used as adressbits. Using b0 to indicate a valid pointer. */
for (cnt = 0; cnt < 0x08; cnt++)
si->engine.fifo.ch_ptr[(si->engine.fifo.handle[cnt])] = (cnt * 0x00002000);
{
si->engine.fifo.ch_ptr[(si->engine.fifo.handle[cnt])] =
(0x00000001 + (cnt * 0x00002000));
}
/* init DMA command buffer pointer */
si->engine.dma.cmdbuffer = (uint32 *)((char *)si->framebuffer +
@ -639,9 +644,6 @@ status_t nv_acc_init_dma()
si->engine.dma.cmdbuffer[0x0f] =
(0x80000000 | si->engine.fifo.handle[0]);
/* initialize our local pointers */
nv_acc_assert_fifo_dma();
/* we have issued no DMA cmd's to the engine yet: the above ones are still
* awaiting execution start. */
si->engine.dma.put = 0;
@ -656,6 +658,9 @@ status_t nv_acc_init_dma()
/* note the current free space we have left in the DMA buffer */
si->engine.dma.free = /*si->dma.*/max - si->engine.dma.current /*+ 1*/;
/* initialize our local pointers */
nv_acc_assert_fifo_dma();
//fixme: add colorspace and buffer config cmd's or predefine in the non-DMA way.
//fixme: overlay should stay outside the DMA buffer, also add a failsafe
// space in between both functions as errors might hang the engine!
@ -712,7 +717,7 @@ static status_t nv_acc_fifofree_dma(uint16 cmd_size)
static void nv_acc_cmd_dma(uint32 cmd, uint16 offset, uint16 size)
{
si->engine.dma.cmdbuffer[si->engine.dma.current++] = ((size << 18) |
(si->engine.fifo.ch_ptr[cmd] + offset));
((si->engine.fifo.ch_ptr[cmd] & 0x0000fffc) + offset));
}
/* fixme? (check this out..)
@ -755,10 +760,12 @@ static void nv_acc_assert_fifo_dma(void)
si->engine.fifo.handle[5] = NV3_GDI_RECTANGLE_TEXT;
/* set handle's pointers to their assigned FIFO channels */
/* note:
* b0-1 aren't used as adressbits. Using b0 to indicate a valid pointer. */
for (cnt = 0; cnt < 0x08; cnt++)
{
si->engine.fifo.ch_ptr[(si->engine.fifo.handle[cnt])] =
(cnt * 0x00002000);
(0x00000001 + (cnt * 0x00002000));
}
/* program new FIFO assignments */