2018-03-10 15:29:35 +03:00
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/*
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* Copyright 2018, Jaroslaw Pelczar <jarek@jpelczar.com>
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* Distributed under the terms of the MIT License.
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*/
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#ifndef _KERNEL_ARCH_ARM64_ARCH_CPU_H_
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#define _KERNEL_ARCH_ARM64_ARCH_CPU_H_
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#define CPU_MAX_CACHE_LEVEL 8
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#define CACHE_LINE_SIZE 64
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#define set_ac()
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#define clear_ac()
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2019-08-31 00:04:29 +03:00
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#include <kernel/arch/arm64/arm_registers.h>
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2018-03-10 15:29:35 +03:00
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#ifndef _ASSEMBLER
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#include <arch/arm64/arch_thread_types.h>
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#include <kernel.h>
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#define arm64_sev() __asm__ __volatile__("sev" : : : "memory")
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#define arm64_wfe() __asm__ __volatile__("wfe" : : : "memory")
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#define arm64_dsb() __asm__ __volatile__("dsb" : : : "memory")
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#define arm64_dmb() __asm__ __volatile__("dmb" : : : "memory")
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#define arm64_isb() __asm__ __volatile__("isb" : : : "memory")
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#define arm64_nop() __asm__ __volatile__("nop" : : : "memory")
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#define arm64_yield() __asm__ __volatile__("yield" : : : "memory")
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/* Extract CPU affinity levels 0-3 */
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#define CPU_AFF0(mpidr) (u_int)(((mpidr) >> 0) & 0xff)
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#define CPU_AFF1(mpidr) (u_int)(((mpidr) >> 8) & 0xff)
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#define CPU_AFF2(mpidr) (u_int)(((mpidr) >> 16) & 0xff)
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#define CPU_AFF3(mpidr) (u_int)(((mpidr) >> 32) & 0xff)
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#define CPU_AFF0_MASK 0xffUL
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#define CPU_AFF1_MASK 0xff00UL
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#define CPU_AFF2_MASK 0xff0000UL
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#define CPU_AFF3_MASK 0xff00000000UL
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#define CPU_AFF_MASK (CPU_AFF0_MASK | CPU_AFF1_MASK | \
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CPU_AFF2_MASK| CPU_AFF3_MASK) /* Mask affinity fields in MPIDR_EL1 */
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#define CPU_IMPL_ARM 0x41
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#define CPU_IMPL_BROADCOM 0x42
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#define CPU_IMPL_CAVIUM 0x43
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#define CPU_IMPL_DEC 0x44
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#define CPU_IMPL_INFINEON 0x49
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#define CPU_IMPL_FREESCALE 0x4D
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#define CPU_IMPL_NVIDIA 0x4E
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#define CPU_IMPL_APM 0x50
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#define CPU_IMPL_QUALCOMM 0x51
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#define CPU_IMPL_MARVELL 0x56
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#define CPU_IMPL_INTEL 0x69
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#define CPU_PART_THUNDER 0x0A1
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#define CPU_PART_FOUNDATION 0xD00
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#define CPU_PART_CORTEX_A35 0xD04
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#define CPU_PART_CORTEX_A53 0xD03
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#define CPU_PART_CORTEX_A55 0xD05
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#define CPU_PART_CORTEX_A57 0xD07
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#define CPU_PART_CORTEX_A72 0xD08
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#define CPU_PART_CORTEX_A73 0xD09
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#define CPU_PART_CORTEX_A75 0xD0A
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#define CPU_REV_THUNDER_1_0 0x00
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#define CPU_REV_THUNDER_1_1 0x01
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#define CPU_IMPL(midr) (((midr) >> 24) & 0xff)
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#define CPU_PART(midr) (((midr) >> 4) & 0xfff)
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#define CPU_VAR(midr) (((midr) >> 20) & 0xf)
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#define CPU_REV(midr) (((midr) >> 0) & 0xf)
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#define CPU_IMPL_TO_MIDR(val) (((val) & 0xff) << 24)
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#define CPU_PART_TO_MIDR(val) (((val) & 0xfff) << 4)
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#define CPU_VAR_TO_MIDR(val) (((val) & 0xf) << 20)
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#define CPU_REV_TO_MIDR(val) (((val) & 0xf) << 0)
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#define CPU_IMPL_MASK (0xff << 24)
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#define CPU_PART_MASK (0xfff << 4)
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#define CPU_VAR_MASK (0xf << 20)
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#define CPU_REV_MASK (0xf << 0)
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#define CPU_ID_RAW(impl, part, var, rev) \
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(CPU_IMPL_TO_MIDR((impl)) | \
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CPU_PART_TO_MIDR((part)) | CPU_VAR_TO_MIDR((var)) | \
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CPU_REV_TO_MIDR((rev)))
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#define CPU_MATCH(mask, impl, part, var, rev) \
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(((mask) & PCPU_GET(midr)) == \
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((mask) & CPU_ID_RAW((impl), (part), (var), (rev))))
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#define CPU_MATCH_RAW(mask, devid) \
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(((mask) & PCPU_GET(midr)) == ((mask) & (devid)))
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static inline uint64 arm64_get_cyclecount(void)
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{
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return READ_SPECIALREG(cntvct_el0);
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}
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#define ADDRESS_TRANSLATE_FUNC(stage) \
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static inline uint64 \
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arm64_address_translate_ ##stage (uint64 addr) \
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{ \
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uint64 ret; \
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\
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__asm __volatile( \
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2019-08-31 00:04:29 +03:00
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"at " __ARMREG_STRING(stage) ", %1 \n" \
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2018-03-10 15:29:35 +03:00
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"mrs %0, par_el1" : "=r"(ret) : "r"(addr)); \
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\
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return (ret); \
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}
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2022-03-27 23:15:03 +03:00
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2018-03-10 15:29:35 +03:00
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ADDRESS_TRANSLATE_FUNC(s1e0r)
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ADDRESS_TRANSLATE_FUNC(s1e0w)
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ADDRESS_TRANSLATE_FUNC(s1e1r)
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ADDRESS_TRANSLATE_FUNC(s1e1w)
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2022-03-27 23:15:03 +03:00
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struct aarch64_fpu_state
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{
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uint64 regs[32 * 2];
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uint64 fpsr;
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uint64 fpcr;
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};
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2018-03-10 15:29:35 +03:00
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/* raw exception frames */
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struct iframe {
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2022-03-27 23:15:03 +03:00
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// return info
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uint64 elr;
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uint64 spsr;
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uint64 x[20];
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uint64 lr;
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uint64 sp;
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// exception info
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uint64 esr;
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uint64 far;
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2018-03-10 15:29:35 +03:00
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};
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2022-03-27 23:15:03 +03:00
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2019-08-31 00:04:29 +03:00
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#ifdef __cplusplus
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2018-03-10 15:29:35 +03:00
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namespace BKernel {
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struct Thread;
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} // namespace BKernel
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2022-03-27 23:15:03 +03:00
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2018-03-10 15:29:35 +03:00
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typedef struct arch_cpu_info {
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uint32 mpidr;
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BKernel::Thread* last_vfp_user;
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} arch_cpu_info;
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2019-08-31 00:04:29 +03:00
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#endif
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2018-03-10 15:29:35 +03:00
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2022-03-27 23:15:03 +03:00
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2018-03-10 15:29:35 +03:00
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#ifdef __cplusplus
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extern "C" {
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#endif
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2022-03-27 23:15:03 +03:00
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2018-03-10 15:29:35 +03:00
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static inline void arch_cpu_pause(void)
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{
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arm64_yield();
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}
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2022-03-27 23:15:03 +03:00
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2018-03-10 15:29:35 +03:00
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static inline void arch_cpu_idle(void)
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{
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arm64_yield();
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}
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2022-03-27 23:15:03 +03:00
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2018-03-10 15:29:35 +03:00
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif /* _KERNEL_ARCH_ARM64_ARCH_CPU_H_ */
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