arm64: Add exception handling, handle pagetables access and dirty flags.
Change-Id: I751d78eb458da16098d236f3829d0c26540fbc17 Reviewed-on: https://review.haiku-os.org/c/haiku/+/5264 Reviewed-by: Adrien Destugues <pulkomandy@gmail.com> Reviewed-by: waddlesplash <waddlesplash@gmail.com> Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
This commit is contained in:
milek7
waddlesplash
parent
78ea9ffc9b
commit
d1c3213a6d
@ -110,46 +110,66 @@ arm64_address_translate_ ##stage (uint64 addr) \
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return (ret); \
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}
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ADDRESS_TRANSLATE_FUNC(s1e0r)
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ADDRESS_TRANSLATE_FUNC(s1e0w)
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ADDRESS_TRANSLATE_FUNC(s1e1r)
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ADDRESS_TRANSLATE_FUNC(s1e1w)
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struct aarch64_fpu_state
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{
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uint64 regs[32 * 2];
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uint64 fpsr;
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uint64 fpcr;
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};
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/* raw exception frames */
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struct iframe {
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uint64 sp;
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uint64 lr;
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uint64 elr;
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uint32 spsr;
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uint32 esr;
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uint64 x[30];
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// return info
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uint64 elr;
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uint64 spsr;
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uint64 x[20];
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uint64 lr;
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uint64 sp;
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// exception info
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uint64 esr;
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uint64 far;
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};
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#ifdef __cplusplus
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namespace BKernel {
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struct Thread;
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} // namespace BKernel
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typedef struct arch_cpu_info {
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uint32 mpidr;
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BKernel::Thread* last_vfp_user;
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} arch_cpu_info;
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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static inline void arch_cpu_pause(void)
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{
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arm64_yield();
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}
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static inline void arch_cpu_idle(void)
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{
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arm64_yield();
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}
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#ifdef __cplusplus
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}
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#endif
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@ -15,7 +15,7 @@
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static inline void
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arch_int_enable_interrupts_inline(void)
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{
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__asm__ __volatile__("msr daifclr, #2");
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asm volatile("msr daifclr, #0xf" : : : "memory");
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}
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@ -24,10 +24,7 @@ arch_int_disable_interrupts_inline(void)
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{
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uint32 flags;
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__asm__ __volatile__(
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"mrs %0, daif\n\t"
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"msr daifset, #2\n\t"
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: "=&r"(flags));
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asm volatile("mrs %0, daif\n" "msr daifset, #0xf" : "=r"(flags) : : "memory");
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return flags;
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}
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@ -36,22 +33,17 @@ arch_int_disable_interrupts_inline(void)
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static inline void
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arch_int_restore_interrupts_inline(int oldState)
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{
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WRITE_SPECIALREG(daif, oldState);
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asm volatile("msr daif, %0" : : "r"(oldState) : "memory");
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}
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static inline bool
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arch_int_are_interrupts_enabled_inline(void)
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{
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uint32 flags;
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__asm__ __volatile__(
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"mrs %0, daif\n\t"
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: "=&r"(flags));
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return (flags & PSR_I) == 0;
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return (READ_SPECIALREG(DAIF) & PSR_I) == 0;
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}
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// map the functions to the inline versions
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#define arch_int_enable_interrupts() arch_int_enable_interrupts_inline()
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#define arch_int_disable_interrupts() arch_int_disable_interrupts_inline()
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@ -60,4 +52,5 @@ arch_int_are_interrupts_enabled_inline(void)
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#define arch_int_are_interrupts_enabled() \
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arch_int_are_interrupts_enabled_inline()
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#endif /* _KERNEL_ARCH_ARM64_ARCH_INT_H_ */
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@ -38,3 +38,5 @@ KernelMergeObject kernel_arch_arm64.o :
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$(TARGET_KERNEL_PIC_CCFLAGS) -Wno-unused
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:
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;
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CreateAsmStructOffsetsHeader asm_offsets.h : asm_offsets.cpp : $(TARGET_KERNEL_ARCH) ;
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@ -4,9 +4,237 @@
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*/
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#include <arch/arm/arch_cpu.h>
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#include <asm_defs.h>
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#include "asm_offsets.h"
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.text
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.macro xchg_sp xt
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add sp, sp, \xt
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sub \xt, sp, \xt
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sub sp, sp, \xt
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.endm
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.macro EXCEPTION_ENTRY el
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// interrupts are automatically disabled by hardware
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// avoid using sp in case it is misaligned
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// swap sp with x19 and use it instead
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xchg_sp x19
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// x19 is now the stack top, make room for IFRAME
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sub x19, x19, #(IFRAME_sizeof)
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stp x0, x1, [x19, #(IFRAME_x + 0 * 8)]
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stp x2, x3, [x19, #(IFRAME_x + 2 * 8)]
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stp x4, x5, [x19, #(IFRAME_x + 4 * 8)]
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stp x6, x7, [x19, #(IFRAME_x + 6 * 8)]
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stp x8, x9, [x19, #(IFRAME_x + 8 * 8)]
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stp x10, x11, [x19, #(IFRAME_x + 10 * 8)]
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stp x12, x13, [x19, #(IFRAME_x + 12 * 8)]
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stp x14, x15, [x19, #(IFRAME_x + 14 * 8)]
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stp x16, x17, [x19, #(IFRAME_x + 16 * 8)]
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mov x0, sp // original x19 that we swapped with sp
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stp x18, x0, [x19, #(IFRAME_x + 18 * 8)]
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// x20-x29 won't be clobbered
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// thus we don't really need to store these
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str x30, [x19, #(IFRAME_lr)]
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.if \el == 0
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mrs x0, SP_EL0
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.else
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// add sizeof back here to store original sp
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add x0, x19, #(IFRAME_sizeof)
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.endif
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mrs x1, ELR_EL1
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mrs x2, SPSR_EL1
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mrs x3, ESR_EL1
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mrs x4, FAR_EL1
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str x0, [x19, #(IFRAME_sp)]
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str x1, [x19, #(IFRAME_elr)]
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str x2, [x19, #(IFRAME_spsr)]
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str x3, [x19, #(IFRAME_esr)]
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str x4, [x19, #(IFRAME_far)]
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.endm
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.macro EXCEPTION_RETURN el
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// x19 is callee-saved so it still points to IFRAME
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// x0, x1, x18, x19 will be restored at the very end
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ldr x0, [x19, #(IFRAME_elr)]
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ldr x1, [x19, #(IFRAME_spsr)]
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ldr x18, [x19, #(IFRAME_sp)]
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// x0 and x1 will be restored later
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ldp x2, x3, [x19, #(IFRAME_x + 2 * 8)]
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ldp x4, x5, [x19, #(IFRAME_x + 4 * 8)]
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ldp x6, x7, [x19, #(IFRAME_x + 6 * 8)]
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ldp x8, x9, [x19, #(IFRAME_x + 8 * 8)]
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ldp x10, x11, [x19, #(IFRAME_x + 10 * 8)]
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ldp x12, x13, [x19, #(IFRAME_x + 12 * 8)]
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ldp x14, x15, [x19, #(IFRAME_x + 14 * 8)]
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ldp x16, x17, [x19, #(IFRAME_x + 16 * 8)]
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// x18 and x19 will be restored later
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ldr x30, [x19, #(IFRAME_lr)]
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// disable interrupts before restoring ELR/SPSR/sp
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msr DAIFSet, #0xf
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msr ELR_EL1, x0
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msr SPSR_EL1, x1
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.if \el == 0
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// load stack pointer for EL0 from IFRAME
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msr SP_EL0, x18
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// unwind our own stack pointer
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add sp, x19, #(IFRAME_sizeof)
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.else
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// we stored original pointer to IFRAME, no need to unwind again there
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mov sp, x18
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.endif
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// finally restore remaining registers
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ldp x0, x1, [x19, #(IFRAME_x + 0 * 8)]
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ldp x18, x19, [x19, #(IFRAME_x + 18 * 8)]
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eret
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.endm
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.macro EXCEPTION_HANDLER el name func
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FUNCTION(handle_\name):
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EXCEPTION_ENTRY \el
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// prepare aligned sp for C function
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and sp, x19, #0xfffffffffffffff0
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// call C handler, passing IFRAME in x0
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// handler can enable interrupts if it wants to
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mov x0, x19
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bl \func
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EXCEPTION_RETURN \el
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FUNCTION_END(handle_\name)
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.endm
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.macro vector name
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.align 7
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b handle_\name
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.endm
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.macro vempty
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.align 7
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brk 0xfff
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1: b 1b
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.endm
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.align 11
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.globl _exception_vectors
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_exception_vectors:
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vempty /* Synchronous EL1t */
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vempty /* IRQ EL1t */
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vempty /* FIQ EL1t */
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vempty /* Error EL1t */
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vector el1h_sync /* Synchronous EL1h */
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vector el1h_irq /* IRQ EL1h */
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vector el1h_fiq /* FIQ EL1h */
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vector el1h_error /* Error EL1h */
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vector el0_sync /* Synchronous 64-bit EL0 */
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vector el0_irq /* IRQ 64-bit EL0 */
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vector el0_fiq /* FIQ 64-bit EL0 */
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vector el0_error /* Error 64-bit EL0 */
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vempty /* Synchronous 32-bit EL0 */
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vempty /* IRQ 32-bit EL0 */
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vempty /* FIQ 32-bit EL0 */
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vempty /* Error 32-bit EL0 */
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EXCEPTION_HANDLER 1 el1h_sync do_sync_handler
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EXCEPTION_HANDLER 1 el1h_irq do_irq_handler
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EXCEPTION_HANDLER 1 el1h_fiq do_fiq_handler
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EXCEPTION_HANDLER 1 el1h_error do_error_handler
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EXCEPTION_HANDLER 0 el0_sync do_sync_handler
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EXCEPTION_HANDLER 0 el0_irq do_irq_handler
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EXCEPTION_HANDLER 0 el0_fiq do_fiq_handler
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EXCEPTION_HANDLER 0 el0_error do_error_handler
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FUNCTION(_eret_with_iframe):
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mov x20, xzr
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mov x21, xzr
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mov x22, xzr
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mov x23, xzr
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mov x24, xzr
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mov x25, xzr
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mov x26, xzr
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mov x27, xzr
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mov x28, xzr
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mov x29, xzr
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mov x19, x0
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EXCEPTION_RETURN 0
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FUNCTION_END(_eret_with_iframe)
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FUNCTION(_fp_save):
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stp q0, q1, [x0], #32
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stp q2, q3, [x0], #32
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stp q4, q5, [x0], #32
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stp q6, q7, [x0], #32
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stp q8, q9, [x0], #32
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stp q10, q11, [x0], #32
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stp q12, q13, [x0], #32
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stp q14, q15, [x0], #32
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stp q16, q17, [x0], #32
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stp q18, q19, [x0], #32
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stp q20, q21, [x0], #32
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stp q22, q23, [x0], #32
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stp q24, q25, [x0], #32
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stp q26, q27, [x0], #32
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stp q28, q29, [x0], #32
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stp q30, q31, [x0], #32
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mrs x1, FPSR
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mrs x2, FPCR
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str x1, [x0], #8
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str x2, [x0], #8
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ret
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FUNCTION_END(_fp_save)
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FUNCTION(_fp_restore):
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ldp q0, q1, [x0], #32
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ldp q2, q3, [x0], #32
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ldp q4, q5, [x0], #32
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ldp q6, q7, [x0], #32
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ldp q8, q9, [x0], #32
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ldp q10, q11, [x0], #32
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ldp q12, q13, [x0], #32
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ldp q14, q15, [x0], #32
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ldp q16, q17, [x0], #32
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ldp q18, q19, [x0], #32
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ldp q20, q21, [x0], #32
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ldp q22, q23, [x0], #32
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ldp q24, q25, [x0], #32
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ldp q26, q27, [x0], #32
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ldp q28, q29, [x0], #32
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ldp q30, q31, [x0], #32
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ldr x1, [x0], #8
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msr FPSR, x1
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// avoid restoring FPCR if it hasn't changed
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ldr x2, [x0], #8
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mrs x3, FPCR
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cmp x3, x2
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beq 1f
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msr FPCR, x2
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1:
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ret
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FUNCTION_END(_fp_restore)
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FUNCTION(_arch_context_swap):
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stp x19, x20, [x0], #16
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stp x21, x22, [x0], #16
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@ -32,24 +260,6 @@ FUNCTION(_arch_context_swap):
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ret
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FUNCTION_END(_arch_context_swap)
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/* status_t arch_cpu_user_memcpy(void *to, const void *from, size_t size, addr_t *faultHandler) */
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FUNCTION(_arch_cpu_user_memcpy):
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mov x0, xzr
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ret
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FUNCTION_END(_arch_cpu_user_memcpy)
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/* status_t arch_cpu_user_memset(void *to, char c, size_t count, addr_t *faultHandler) */
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FUNCTION(_arch_cpu_user_memset):
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mov x0, xzr
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ret
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FUNCTION_END(_arch_cpu_user_memset)
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/* ssize_t arch_cpu_user_strlcpy(void *to, const void *from, size_t size, addr_t *faultHandler) */
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FUNCTION(_arch_cpu_user_strlcpy):
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mov x0, xzr
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ret
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FUNCTION_END(_arch_cpu_user_strlcpy)
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/*! \fn void arch_debug_call_with_fault_handler(cpu_ent* cpu,
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jmp_buf jumpBuffer, void (*function)(void*), void* parameter)
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@ -68,6 +278,15 @@ FUNCTION_END(_arch_cpu_user_strlcpy)
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\param parameter The parameter to be passed to the function to be called.
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*/
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FUNCTION(arch_debug_call_with_fault_handler):
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mov x0, xzr
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ret
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ldr x4, =fault
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str x4, [x0, #CPU_ENT_fault_handler]
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str x1, [x0, #CPU_ENT_fault_handler_stack_pointer]
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mov x0, x3
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br x2
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fault:
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mov x0, sp
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mov x1, #1
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b longjmp
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FUNCTION_END(arch_debug_call_with_fault_handler)
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@ -12,9 +12,13 @@
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#include <elf.h>
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extern "C" void _exception_vectors(void);
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status_t
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arch_cpu_preboot_init_percpu(kernel_args *args, int curr_cpu)
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{
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WRITE_SPECIALREG(VBAR_EL1, _exception_vectors);
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return B_OK;
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}
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@ -8,15 +8,19 @@
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#include <boot/kernel_args.h>
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#include <device_manager.h>
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#include <kscheduler.h>
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#include <ksyscalls.h>
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#include <interrupt_controller.h>
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#include <smp.h>
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#include <thread.h>
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#include <timer.h>
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#include <util/AutoLock.h>
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#include <util/DoublyLinkedList.h>
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#include <util/kernel_cpp.h>
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#include <vm/vm.h>
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#include <vm/vm_priv.h>
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#include <vm/VMAddressSpace.h>
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#include "syscall_numbers.h"
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#include "VMSAv8TranslationMap.h"
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#include <string.h>
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#define TRACE_ARCH_INT
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@ -73,3 +77,240 @@ arch_int_init_post_device_manager(struct kernel_args *args)
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{
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return B_ENTRY_NOT_FOUND;
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}
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// TODO: reuse things from VMSAv8TranslationMap
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static int page_bits = 12;
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static constexpr uint64_t kPteAddrMask = (((1UL << 36) - 1) << 12);
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static constexpr uint64_t kPteAttrMask = ~(kPteAddrMask | 0x3);
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static constexpr uint64_t kAttrSWDBM = (1UL << 55);
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static constexpr uint64_t kAttrAF = (1UL << 10);
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static constexpr uint64_t kAttrAP2 = (1UL << 7);
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static uint64_t*
|
||||
TableFromPa(phys_addr_t pa)
|
||||
{
|
||||
return reinterpret_cast<uint64_t*>(KERNEL_PMAP_BASE + pa);
|
||||
}
|
||||
|
||||
|
||||
static bool
|
||||
fixup_entry(phys_addr_t ptPa, int level, addr_t va, bool wr)
|
||||
{
|
||||
int tableBits = page_bits - 3;
|
||||
uint64_t tableMask = (1UL << tableBits) - 1;
|
||||
|
||||
int shift = tableBits * (3 - level) + page_bits;
|
||||
uint64_t entrySize = 1UL << shift;
|
||||
uint64_t entryMask = entrySize - 1;
|
||||
|
||||
int index = (va >> shift) & tableMask;
|
||||
|
||||
uint64_t *pte = &TableFromPa(ptPa)[index];
|
||||
|
||||
int type = *pte & 0x3;
|
||||
uint64_t addr = *pte & kPteAddrMask;
|
||||
|
||||
if ((level == 3 && type == 0x3) || (level < 3 && type == 0x1)) {
|
||||
if (!wr && (*pte & kAttrAF) == 0) {
|
||||
atomic_or64((int64*)pte, kAttrAF);
|
||||
return true;
|
||||
}
|
||||
if (wr && (*pte & kAttrSWDBM) != 0 && (*pte & kAttrAP2) != 0) {
|
||||
atomic_and64((int64*)pte, ~kAttrAP2);
|
||||
asm("tlbi vaae1is, %0 \n dsb ish"::"r"(va >> page_bits));
|
||||
return true;
|
||||
}
|
||||
} else if (level < 3 && type == 0x3) {
|
||||
return fixup_entry(addr, level + 1, va, wr);
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
after_exception()
|
||||
{
|
||||
Thread* thread = thread_get_current_thread();
|
||||
if (thread->cpu->invoke_scheduler) {
|
||||
disable_interrupts();
|
||||
SpinLocker schedulerLocker(thread->scheduler_lock);
|
||||
scheduler_reschedule(B_THREAD_READY);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
extern "C" void
|
||||
do_sync_handler(iframe * frame)
|
||||
{
|
||||
bool isExec = false;
|
||||
switch (ESR_ELx_EXCEPTION(frame->esr)) {
|
||||
case EXCP_INSN_ABORT_L:
|
||||
case EXCP_INSN_ABORT:
|
||||
isExec = true;
|
||||
case EXCP_DATA_ABORT_L:
|
||||
case EXCP_DATA_ABORT:
|
||||
{
|
||||
bool write = (frame->esr & ISS_DATA_WnR) != 0;
|
||||
bool known = false;
|
||||
|
||||
int initialLevel = VMSAv8TranslationMap::CalcStartLevel(48, 12);
|
||||
phys_addr_t ptPa;
|
||||
bool addrType = (frame->far & (1UL << 63)) != 0;
|
||||
if (addrType)
|
||||
ptPa = READ_SPECIALREG(TTBR1_EL1);
|
||||
else
|
||||
ptPa = READ_SPECIALREG(TTBR0_EL1);
|
||||
|
||||
switch (frame->esr & ISS_DATA_DFSC_MASK) {
|
||||
case ISS_DATA_DFSC_TF_L0:
|
||||
case ISS_DATA_DFSC_TF_L1:
|
||||
case ISS_DATA_DFSC_TF_L2:
|
||||
case ISS_DATA_DFSC_TF_L3:
|
||||
known = true;
|
||||
break;
|
||||
|
||||
case ISS_DATA_DFSC_AFF_L1:
|
||||
case ISS_DATA_DFSC_AFF_L2:
|
||||
case ISS_DATA_DFSC_AFF_L3:
|
||||
known = true;
|
||||
if (fixup_entry(ptPa, initialLevel, frame->far, false))
|
||||
return;
|
||||
break;
|
||||
|
||||
case ISS_DATA_DFSC_PF_L1:
|
||||
case ISS_DATA_DFSC_PF_L2:
|
||||
case ISS_DATA_DFSC_PF_L3:
|
||||
known = true;
|
||||
if (write && fixup_entry(ptPa, initialLevel, frame->far, true))
|
||||
return;
|
||||
break;
|
||||
}
|
||||
|
||||
if (!known)
|
||||
break;
|
||||
|
||||
if (debug_debugger_running()) {
|
||||
Thread* thread = thread_get_current_thread();
|
||||
if (thread != NULL) {
|
||||
cpu_ent* cpu = &gCPU[smp_get_current_cpu()];
|
||||
if (cpu->fault_handler != 0) {
|
||||
debug_set_page_fault_info(frame->far, frame->elr,
|
||||
write ? DEBUG_PAGE_FAULT_WRITE : 0);
|
||||
frame->elr = cpu->fault_handler;
|
||||
frame->sp = cpu->fault_handler_stack_pointer;
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Thread *thread = thread_get_current_thread();
|
||||
ASSERT(thread);
|
||||
|
||||
bool isUser = (frame->spsr & PSR_M_MASK) == PSR_M_EL0t;
|
||||
|
||||
if ((frame->spsr & PSR_I) != 0) {
|
||||
// interrupts disabled
|
||||
uintptr_t handler = reinterpret_cast<uintptr_t>(thread->fault_handler);
|
||||
if (thread->fault_handler != 0) {
|
||||
frame->elr = handler;
|
||||
return;
|
||||
}
|
||||
} else if (thread->page_faults_allowed != 0) {
|
||||
dprintf("PF: %lx\n", frame->far);
|
||||
enable_interrupts();
|
||||
addr_t ret = 0;
|
||||
vm_page_fault(frame->far, frame->elr, write, isExec, isUser, &ret);
|
||||
if (ret != 0)
|
||||
frame->elr = ret;
|
||||
return;
|
||||
}
|
||||
|
||||
panic("unhandled pagefault! FAR=%lx ELR=%lx ESR=%lx",
|
||||
frame->far, frame->elr, frame->esr);
|
||||
break;
|
||||
}
|
||||
|
||||
case EXCP_SVC64:
|
||||
{
|
||||
uint32 imm = (frame->esr & 0xffff);
|
||||
|
||||
uint32 count = imm & 0x1f;
|
||||
uint32 syscall = imm >> 5;
|
||||
|
||||
uint64_t args[20];
|
||||
if (count > 20) {
|
||||
frame->x[0] = B_ERROR;
|
||||
return;
|
||||
}
|
||||
|
||||
memset(args, 0, sizeof(args));
|
||||
memcpy(args, frame->x, (count < 8 ? count : 8) * 8);
|
||||
|
||||
if (count > 8) {
|
||||
if (!IS_USER_ADDRESS(frame->sp)
|
||||
|| user_memcpy(&args[8], (void*)frame->sp, (count - 8) * 8) != B_OK) {
|
||||
frame->x[0] = B_BAD_ADDRESS;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
thread_at_kernel_entry(system_time());
|
||||
|
||||
enable_interrupts();
|
||||
syscall_dispatcher(syscall, (void*)args, &frame->x[0]);
|
||||
|
||||
{
|
||||
disable_interrupts();
|
||||
atomic_and(&thread_get_current_thread()->flags, ~THREAD_FLAGS_SYSCALL_RESTARTED);
|
||||
if ((thread_get_current_thread()->flags
|
||||
& (THREAD_FLAGS_SIGNALS_PENDING
|
||||
| THREAD_FLAGS_DEBUG_THREAD
|
||||
| THREAD_FLAGS_TRAP_FOR_CORE_DUMP)) != 0) {
|
||||
enable_interrupts();
|
||||
thread_at_kernel_exit();
|
||||
} else {
|
||||
thread_at_kernel_exit_no_signals();
|
||||
}
|
||||
if ((THREAD_FLAGS_RESTART_SYSCALL & thread_get_current_thread()->flags) != 0) {
|
||||
panic("syscall restart");
|
||||
}
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
panic("unhandled exception! FAR=%lx ELR=%lx ESR=%lx (EC=%lx)",
|
||||
frame->far, frame->elr, frame->esr, (frame->esr >> 26) & 0x3f);
|
||||
}
|
||||
|
||||
|
||||
extern "C" void
|
||||
do_error_handler(iframe * frame)
|
||||
{
|
||||
panic("unhandled error! FAR=%lx ELR=%lx ESR=%lx", frame->far, frame->elr, frame->esr);
|
||||
}
|
||||
|
||||
|
||||
extern "C" void
|
||||
do_irq_handler(iframe * frame)
|
||||
{
|
||||
InterruptController *ic = InterruptController::Get();
|
||||
if (ic != NULL)
|
||||
ic->HandleInterrupt();
|
||||
|
||||
after_exception();
|
||||
}
|
||||
|
||||
|
||||
extern "C" void
|
||||
do_fiq_handler(iframe * frame)
|
||||
{
|
||||
panic("do_fiq_handler");
|
||||
}
|
||||
|
||||
44
src/system/kernel/arch/arm64/asm_offsets.cpp
Normal file
44
src/system/kernel/arch/arm64/asm_offsets.cpp
Normal file
@ -0,0 +1,44 @@
|
||||
/*
|
||||
* Copyright 2007-2011, Ingo Weinhold, ingo_weinhold@gmx.de.
|
||||
* Distributed under the terms of the MIT License.
|
||||
*/
|
||||
|
||||
// This file is used to get C structure offsets into assembly code.
|
||||
// The build system assembles the file and processes the output to create
|
||||
// a header file with macro definitions, that can be included from assembly
|
||||
// code.
|
||||
|
||||
|
||||
#include <computed_asm_macros.h>
|
||||
|
||||
#include <arch_cpu.h>
|
||||
#include <cpu.h>
|
||||
#include <ksignal.h>
|
||||
#include <ksyscalls.h>
|
||||
#include <thread_types.h>
|
||||
|
||||
|
||||
#define DEFINE_MACRO(macro, value) DEFINE_COMPUTED_ASM_MACRO(macro, value)
|
||||
|
||||
#define DEFINE_OFFSET_MACRO(prefix, structure, member) \
|
||||
DEFINE_MACRO(prefix##_##member, offsetof(struct structure, member));
|
||||
|
||||
#define DEFINE_SIZEOF_MACRO(prefix, structure) \
|
||||
DEFINE_MACRO(prefix##_sizeof, sizeof(struct structure));
|
||||
|
||||
|
||||
void
|
||||
dummy()
|
||||
{
|
||||
DEFINE_SIZEOF_MACRO(IFRAME, iframe);
|
||||
DEFINE_OFFSET_MACRO(IFRAME, iframe, elr);
|
||||
DEFINE_OFFSET_MACRO(IFRAME, iframe, spsr);
|
||||
DEFINE_OFFSET_MACRO(IFRAME, iframe, x);
|
||||
DEFINE_OFFSET_MACRO(IFRAME, iframe, lr);
|
||||
DEFINE_OFFSET_MACRO(IFRAME, iframe, sp);
|
||||
DEFINE_OFFSET_MACRO(IFRAME, iframe, esr);
|
||||
DEFINE_OFFSET_MACRO(IFRAME, iframe, far);
|
||||
|
||||
DEFINE_OFFSET_MACRO(CPU_ENT, cpu_ent, fault_handler);
|
||||
DEFINE_OFFSET_MACRO(CPU_ENT, cpu_ent, fault_handler_stack_pointer);
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user