2004-03-15 03:58:12 +03:00
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/*
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Copyright (c) 2002, Thomas Kurschel
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Part of Radeon kernel driver
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BIOS data structures
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*/
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#ifndef _RADEON_BIOS_H
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#define _RADEON_BIOS_H
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typedef struct {
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uint8 clock_chip_type;
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uint8 struct_size;
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uint8 accelerator_entry;
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uint8 VGA_entry;
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uint16 VGA_table_offset;
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uint16 POST_table_offset;
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uint16 XCLK;
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uint16 MCLK;
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uint8 num_PLL_blocks;
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uint8 size_PLL_blocks;
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uint16 PCLK_ref_freq;
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uint16 PCLK_ref_divider;
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uint32 PCLK_min_freq;
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uint32 PCLK_max_freq;
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uint16 MCLK_ref_freq;
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uint16 MCLK_ref_divider;
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uint32 MCLK_min_freq;
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uint32 MCLK_max_freq;
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uint16 XCLK_ref_freq;
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uint16 XCLK_ref_divider;
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uint32 XCLK_min_freq;
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uint32 XCLK_max_freq;
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} __attribute__ ((packed)) PLL_BLOCK;
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typedef struct {
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uint8 dummy0;
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char name[24]; // 1
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uint16 panel_xres; // 25
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uint16 panel_yres; // 27
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uint8 dummy[15];
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uint16 panel_pwr_delay; // 44
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2006-11-05 04:54:11 +03:00
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uint16 ref_div; // 46
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uint8 post_div; // 48
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uint8 feedback_div; // 49
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uint8 dummy2[14];
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2004-03-15 03:58:12 +03:00
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uint16 fpi_timing_ofs[20]; // 64
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} __attribute__ ((packed)) FPI_BLOCK;
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typedef struct {
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uint16 panel_xres; // 0
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uint16 panel_yres; // 2
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uint8 dummy4[5];
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uint16 dot_clock; // 9
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uint8 dummy11[6];
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uint16 h_total; // 17
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uint16 h_display; // 19
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uint16 h_sync_start; // 21
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uint8 h_sync_width; // 23
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uint16 v_total; // 24
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uint16 v_display; // 26
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uint16 v_sync; // 28
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} __attribute__ ((packed)) FPI_TIMING_BLOCK;
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#endif
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