2004-03-15 03:58:12 +03:00
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/*
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Copyright (c) 2002, Thomas Kurschel
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Part of Radeon driver
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BusMemory Control registers
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*/
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#ifndef _MEMCNTRL_REGS_H
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#define _MEMCNTRL_REGS_H
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#define RADEON_AGP_BASE 0x0170
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#define RADEON_MEM_CNTL 0x0140
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#define RADEON_MC_AGP_LOCATION 0x014c
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#define RADEON_MC_FB_LOCATION 0x0148
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#define RADEON_MEM_INIT_LAT_TIMER 0x0154
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#define RADEON_MEM_SDRAM_MODE_REG 0x0158
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# define RADEON_MEM_CFG_TYPE_MASK (1 << 30)
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# define RADEON_MEM_CFG_SDR (0 << 30)
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# define RADEON_MEM_CFG_DDR (1 << 30)
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2004-07-16 04:46:01 +04:00
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#define RADEON_GC_NB_TOM 0x015c
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#define RADEON_DISPLAY_BASE_ADDRESS 0x023c
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#define RADEON_CRTC2_DISPLAY_BASE_ADDRESS 0x033c
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#define RADEON_OV0_BASE_ADDRESS 0x043c
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2004-03-15 03:58:12 +03:00
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#endif
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