2004-03-15 03:58:12 +03:00
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/*
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Copyright (c) 2002, Thomas Kurschel
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Part of Radeon driver
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Unsorted list of remaining Radeon registers
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*/
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#ifndef _RADEON_REGS_H
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#define _RADEON_REGS_H
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#define RADEON_AMCGPIO_A_REG 0x01a0
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#define RADEON_AMCGPIO_EN_REG 0x01a8
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#define RADEON_AMCGPIO_MASK 0x0194
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#define RADEON_AMCGPIO_Y_REG 0x01a4
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#define RADEON_ATTRDR 0x03c1 /* VGA */
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#define RADEON_ATTRDW 0x03c0 /* VGA */
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#define RADEON_ATTRX 0x03c0 /* VGA */
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#define RADEON_AUX_SC_CNTL 0x1660
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# define RADEON_AUX1_SC_EN (1 << 0)
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# define RADEON_AUX1_SC_MODE_OR (0 << 1)
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# define RADEON_AUX1_SC_MODE_NAND (1 << 1)
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# define RADEON_AUX2_SC_EN (1 << 2)
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# define RADEON_AUX2_SC_MODE_OR (0 << 3)
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# define RADEON_AUX2_SC_MODE_NAND (1 << 3)
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# define RADEON_AUX3_SC_EN (1 << 4)
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# define RADEON_AUX3_SC_MODE_OR (0 << 5)
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# define RADEON_AUX3_SC_MODE_NAND (1 << 5)
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#define RADEON_AUX1_SC_BOTTOM 0x1670
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#define RADEON_AUX1_SC_LEFT 0x1664
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#define RADEON_AUX1_SC_RIGHT 0x1668
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#define RADEON_AUX1_SC_TOP 0x166c
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#define RADEON_AUX2_SC_BOTTOM 0x1680
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#define RADEON_AUX2_SC_LEFT 0x1674
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#define RADEON_AUX2_SC_RIGHT 0x1678
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#define RADEON_AUX2_SC_TOP 0x167c
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#define RADEON_AUX3_SC_BOTTOM 0x1690
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#define RADEON_AUX3_SC_LEFT 0x1684
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#define RADEON_AUX3_SC_RIGHT 0x1688
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#define RADEON_AUX3_SC_TOP 0x168c
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#define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8
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#define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc
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#define RADEON_CLR_CMP_CLR_3D 0x1a24
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#define RADEON_CLR_CMP_CLR_DST 0x15c8
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#define RADEON_CLR_CMP_CLR_SRC 0x15c4
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#define RADEON_CLR_CMP_CNTL 0x15c0
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# define RADEON_SRC_CMP_EQ_COLOR (4 << 0)
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# define RADEON_SRC_CMP_NEQ_COLOR (5 << 0)
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# define RADEON_CLR_CMP_SRC_SOURCE (1 << 24)
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#define RADEON_CLR_CMP_MASK 0x15cc
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# define RADEON_CLR_CMP_MSK 0xffffffff
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#define RADEON_CLR_CMP_MASK_3D 0x1A28
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#define RADEON_COMPOSITE_SHADOW_ID 0x1a0c
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#define RADEON_CONFIG_APER_0_BASE 0x0100
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#define RADEON_CONFIG_APER_1_BASE 0x0104
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#define RADEON_CONFIG_APER_SIZE 0x0108
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#define RADEON_CONFIG_BONDS 0x00e8
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#define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114
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#define RADEON_CONFIG_REG_1_BASE 0x010c
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#define RADEON_CONFIG_REG_APER_SIZE 0x0110
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#define RADEON_CONFIG_XSTRAP 0x00e4
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#define RADEON_CONSTANT_COLOR_C 0x1d34
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# define RADEON_CONSTANT_COLOR_MASK 0x00ffffff
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# define RADEON_CONSTANT_COLOR_ONE 0x00ffffff
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# define RADEON_CONSTANT_COLOR_ZERO 0x00000000
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#define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */
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#define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */
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#define RADEON_TV_DAC_CNTL 0x088c
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# define RADEON_TV_DAC_STD_MASK 0x0300
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# define RADEON_TV_DAC_RDACPD (1 << 24)
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# define RADEON_TV_DAC_GDACPD (1 << 25)
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# define RADEON_TV_DAC_BDACPD (1 << 26)
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#define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820
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#define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824
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#define RADEON_DISP_MISC_CNTL 0x0d00
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# define RADEON_SOFT_RESET_GRPH_PP (1 << 0)
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#define RADEON_DST_BRES_DEC 0x1630
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#define RADEON_DST_BRES_ERR 0x1628
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#define RADEON_DST_BRES_INC 0x162c
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#define RADEON_DST_BRES_LNTH 0x1634
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#define RADEON_DST_BRES_LNTH_SUB 0x1638
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#define RADEON_DST_HEIGHT 0x1410
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#define RADEON_DST_HEIGHT_WIDTH 0x143c
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#define RADEON_DST_HEIGHT_WIDTH_8 0x158c
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#define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4
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#define RADEON_DST_HEIGHT_Y 0x15a0
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#define RADEON_DST_OFFSET 0x1404
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#define RADEON_DST_PITCH 0x1408
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#define RADEON_DST_PITCH_OFFSET_C 0x1c80
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# define RADEON_PITCH_SHIFT 21
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# define RADEON_DST_TILE_LINEAR (0 << 30)
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# define RADEON_DST_TILE_MACRO (1 << 30)
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# define RADEON_DST_TILE_MICRO (2 << 30)
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# define RADEON_DST_TILE_BOTH (3 << 30)
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#define RADEON_DST_WIDTH 0x140c
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#define RADEON_DST_WIDTH_HEIGHT 0x1598
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#define RADEON_DST_WIDTH_X 0x1588
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#define RADEON_DST_WIDTH_X_INCY 0x159c
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#define RADEON_DST_X 0x141c
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#define RADEON_DST_X_SUB 0x15a4
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#define RADEON_DST_X_Y 0x1594
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#define RADEON_DST_Y 0x1420
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#define RADEON_DST_Y_SUB 0x15a8
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#define RADEON_DST_Y_X 0x1438
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#define RADEON_FLUSH_1 0x1704
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#define RADEON_FLUSH_2 0x1708
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#define RADEON_FLUSH_3 0x170c
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#define RADEON_FLUSH_4 0x1710
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#define RADEON_FLUSH_5 0x1714
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#define RADEON_FLUSH_6 0x1718
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#define RADEON_FLUSH_7 0x171c
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#define RADEON_FOG_3D_TABLE_START 0x1810
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#define RADEON_FOG_3D_TABLE_END 0x1814
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#define RADEON_FOG_3D_TABLE_DENSITY 0x181c
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#define RADEON_FOG_TABLE_INDEX 0x1a14
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#define RADEON_FOG_TABLE_DATA 0x1a18
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#define RADEON_GENENB 0x03c3 /* VGA */
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#define RADEON_GENFC_RD 0x03ca /* VGA */
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#define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */
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#define RADEON_GENMO_RD 0x03cc /* VGA */
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#define RADEON_GENMO_WT 0x03c2 /* VGA */
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#define RADEON_GENS0 0x03c2 /* VGA */
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#define RADEON_GENS1 0x03da /* VGA, 0x03ba */
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#define RADEON_GRPH8_DATA 0x03cf /* VGA */
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#define RADEON_GRPH8_IDX 0x03ce /* VGA */
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#define RADEON_GUI_DEBUG0 0x16a0
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#define RADEON_GUI_DEBUG1 0x16a4
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#define RADEON_GUI_DEBUG2 0x16a8
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#define RADEON_GUI_DEBUG3 0x16ac
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#define RADEON_GUI_DEBUG4 0x16b0
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#define RADEON_GUI_DEBUG5 0x16b4
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#define RADEON_GUI_DEBUG6 0x16b8
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#define RADEON_GUI_SCRATCH_REG0 0x15e0
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#define RADEON_GUI_SCRATCH_REG1 0x15e4
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#define RADEON_GUI_SCRATCH_REG2 0x15e8
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#define RADEON_GUI_SCRATCH_REG3 0x15ec
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#define RADEON_GUI_SCRATCH_REG4 0x15f0
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#define RADEON_GUI_SCRATCH_REG5 0x15f4
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#define RADEON_HOST_DATA0 0x17c0
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#define RADEON_HOST_DATA1 0x17c4
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#define RADEON_HOST_DATA2 0x17c8
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#define RADEON_HOST_DATA3 0x17cc
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#define RADEON_HOST_DATA4 0x17d0
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#define RADEON_HOST_DATA5 0x17d4
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#define RADEON_HOST_DATA6 0x17d8
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#define RADEON_HOST_DATA7 0x17dc
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#define RADEON_HOST_DATA_LAST 0x17e0
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#define RADEON_HW_DEBUG 0x0128
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#define RADEON_HW_DEBUG2 0x011c
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#define RADEON_I2C_CNTL_1 0x0094
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#define RADEON_LEAD_BRES_DEC 0x1608
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#define RADEON_LEAD_BRES_LNTH 0x161c
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#define RADEON_LEAD_BRES_LNTH_SUB 0x1624
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#define RADEON_LVDS_PLL_CNTL 0x02d4
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# define RADEON_HSYNC_DELAY_SHIFT 28
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# define RADEON_HSYNC_DELAY_MASK (0xf << 28)
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#define RADEON_MDGPIO_A_REG 0x01ac
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#define RADEON_MDGPIO_EN_REG 0x01b0
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#define RADEON_MDGPIO_MASK 0x0198
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#define RADEON_MDGPIO_Y_REG 0x01b4
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#define RADEON_MEM_STR_CNTL 0x0150
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#define RADEON_MEM_VGA_RP_SEL 0x003c
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#define RADEON_MEM_VGA_WP_SEL 0x0038
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#define RADEON_MM_INDEX 0x0000
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#define RADEON_MPLL_CNTL 0x000e /* PLL */
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#define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */
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#define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */
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#define RADEON_N_VIF_COUNT 0x0248
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#define RADEON_PCI_GART_PAGE 0x017c
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#define RADEON_PLANE_3D_MASK_C 0x1d44
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#define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */
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#define RADEON_SC_BOTTOM 0x164c
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#define RADEON_SC_BOTTOM_RIGHT 0x16f0
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#define RADEON_SC_BOTTOM_RIGHT_C 0x1c8c
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#define RADEON_SC_LEFT 0x1640
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#define RADEON_SC_RIGHT 0x1644
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#define RADEON_SC_TOP 0x1648
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#define RADEON_SC_TOP_LEFT 0x16ec
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#define RADEON_SC_TOP_LEFT_C 0x1c88
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# define RADEON_SC_SIGN_MASK_LO 0x8000
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# define RADEON_SC_SIGN_MASK_HI 0x80000000
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#define RADEON_SEQ8_DATA 0x03c5 /* VGA */
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#define RADEON_SEQ8_IDX 0x03c4 /* VGA */
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#define RADEON_SNAPSHOT_F_COUNT 0x0244
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#define RADEON_SNAPSHOT_VH_COUNTS 0x0240
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#define RADEON_SNAPSHOT_VIF_COUNT 0x024c
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#define RADEON_SRC_OFFSET 0x15ac
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#define RADEON_SRC_PITCH 0x15b0
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#define RADEON_SRC_SC_BOTTOM 0x165c
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#define RADEON_SRC_SC_BOTTOM_RIGHT 0x16f4
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#define RADEON_SRC_SC_RIGHT 0x1654
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#define RADEON_SRC_X 0x1414
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#define RADEON_SRC_X_Y 0x1590
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#define RADEON_SRC_Y 0x1418
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#define RADEON_SRC_Y_X 0x1434
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#define RADEON_SURFACE_CNTL 0x0b00
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# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
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# define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20)
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# define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21)
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#define RADEON_SURFACE0_INFO 0x0b0c
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#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
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#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
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#define RADEON_SURFACE1_INFO 0x0b1c
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#define RADEON_SURFACE1_LOWER_BOUND 0x0b14
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#define RADEON_SURFACE1_UPPER_BOUND 0x0b18
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#define RADEON_SURFACE2_INFO 0x0b2c
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#define RADEON_SURFACE2_LOWER_BOUND 0x0b24
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#define RADEON_SURFACE2_UPPER_BOUND 0x0b28
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#define RADEON_SURFACE3_INFO 0x0b3c
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#define RADEON_SURFACE3_LOWER_BOUND 0x0b34
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#define RADEON_SURFACE3_UPPER_BOUND 0x0b38
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#define RADEON_SURFACE4_INFO 0x0b4c
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#define RADEON_SURFACE4_LOWER_BOUND 0x0b44
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#define RADEON_SURFACE4_UPPER_BOUND 0x0b48
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#define RADEON_SURFACE5_INFO 0x0b5c
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#define RADEON_SURFACE5_LOWER_BOUND 0x0b54
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#define RADEON_SURFACE5_UPPER_BOUND 0x0b58
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#define RADEON_SURFACE6_INFO 0x0b6c
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#define RADEON_SURFACE6_LOWER_BOUND 0x0b64
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#define RADEON_SURFACE6_UPPER_BOUND 0x0b68
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#define RADEON_SURFACE7_INFO 0x0b7c
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#define RADEON_SURFACE7_LOWER_BOUND 0x0b74
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#define RADEON_SURFACE7_UPPER_BOUND 0x0b78
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#define RADEON_SW_SEMAPHORE 0x013c
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#define RADEON_TMDS_CRC 0x02a0
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#define RADEON_TRAIL_BRES_DEC 0x1614
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#define RADEON_TRAIL_BRES_ERR 0x160c
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#define RADEON_TRAIL_BRES_INC 0x1610
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#define RADEON_TRAIL_X 0x1618
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#define RADEON_TRAIL_X_SUB 0x1620
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2005-04-01 18:16:38 +04:00
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#define RADEON_VGA_DDA_CONFIG 0x02e8 // Rage 128 reg
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2004-03-15 03:58:12 +03:00
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#define RADEON_VGA_DDA_ON_OFF 0x02ec
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#define RADEON_VID_BUFFER_CONTROL 0x0900
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#define RADEON_VIDEOMUX_CNTL 0x0190
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#define RADEON_OVR_CLR 0x0230
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#define RADEON_OVR_WID_LEFT_RIGHT 0x0234
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#define RADEON_OVR_WID_TOP_BOTTOM 0x0238
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#define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */
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#define RADEON_XCLK_CNTL 0x000d /* PLL */
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#define RADEON_XDLL_CNTL 0x000c /* PLL */
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#define RADEON_XPLL_CNTL 0x000b /* PLL */
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#endif
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