121 lines
5.1 KiB
C
121 lines
5.1 KiB
C
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/*
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Copyright (c) 2002, Thomas Kurschel
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Part of Radeon driver
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PLL registers and access macros
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*/
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#ifndef _PLL_REG_H
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#define _PLL_REG_H
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#include "mmio.h"
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// atomic updates of PLL clock don't seem to always work and stick, thus
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// the bit never resets. Here - we use our own check by reading back the
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// register we've just wrote to make sure it's got the right value
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#define RADEON_ATOMIC_UPDATE 0 // Use PLL Atomic updates (seems broken)
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// mmio registers
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#define RADEON_CLOCK_CNTL_DATA 0x000c
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#define RADEON_CLOCK_CNTL_INDEX 0x0008
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# define RADEON_PLL_WR_EN (1 << 7)
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# define RADEON_PLL_DIV_SEL_MASK (3 << 8)
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# define RADEON_PLL_DIV_SEL_DIV0 (0 << 8)
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# define RADEON_PLL_DIV_SEL_DIV1 (1 << 8)
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# define RADEON_PLL_DIV_SEL_DIV2 (2 << 8)
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# define RADEON_PLL_DIV_SEL_DIV3 (3 << 8)
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// indirect PLL registers
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#define RADEON_CLK_PIN_CNTL 0x0001
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#define RADEON_PPLL_CNTL 0x0002
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# define RADEON_PPLL_RESET (1 << 0)
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# define RADEON_PPLL_SLEEP (1 << 1)
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# define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16)
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# define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
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# define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18)
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#define RADEON_PPLL_REF_DIV 0x0003
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# define RADEON_PPLL_REF_DIV_MASK 0x03ff
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# define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
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# define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
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#define RADEON_PPLL_DIV_0 0x0004
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#define RADEON_PPLL_DIV_1 0x0005
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#define RADEON_PPLL_DIV_2 0x0006
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#define RADEON_PPLL_DIV_3 0x0007
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# define RADEON_PPLL_FB3_DIV_MASK 0x07ff
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# define RADEON_PPLL_POST3_DIV_MASK 0x00070000
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#define RADEON_VCLK_ECP_CNTL 0x0008
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# define RADEON_VCLK_SRC_SEL_MASK (3 << 0)
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# define RADEON_VCLK_SRC_CPU_CLK (0 << 0)
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# define RADEON_VCLK_SRC_PSCAN_CLK (1 << 0)
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# define RADEON_VCLK_SRC_BYTE_CLK (2 << 0)
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# define RADEON_VCLK_SRC_PPLL_CLK (3 << 0)
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# define RADEON_ECP_DIV_SHIFT 8
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# define RADEON_ECP_DIV_MASK (3 << 8)
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# define RADEON_ECP_DIV_VCLK (0 << 8)
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# define RADEON_ECP_DIV_VCLK_2 (1 << 8)
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#define RADEON_HTOTAL_CNTL 0x0009
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#define RADEON_SCLK_CNTL 0x000d
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# define RADEON_DYN_STOP_LAT_MASK 0x00007ff8
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# define RADEON_CP_MAX_DYN_STOP_LAT 0x0008
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# define RADEON_SCLK_FORCEON_MASK 0xffff8000
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#define RADEON_SCLK_MORE_CNTL 0x0035
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# define RADEON_SCLK_MORE_FORCEON 0x0700
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#define RADEON_MCLK_CNTL 0x0012
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# define RADEON_FORCEON_MCLKA (1 << 16)
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# define RADEON_FORCEON_MCLKB (1 << 17)
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# define RADEON_FORCEON_YCLKA (1 << 18)
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# define RADEON_FORCEON_YCLKB (1 << 19)
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# define RADEON_FORCEON_MC (1 << 20)
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# define RADEON_FORCEON_AIC (1 << 21)
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#define RADEON_P2PLL_CNTL 0x002a
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# define RADEON_P2PLL_RESET (1 << 0)
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# define RADEON_P2PLL_SLEEP (1 << 1)
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# define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16)
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# define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
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# define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18)
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#define RADEON_P2PLL_REF_DIV 0x002B
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# define RADEON_P2PLL_REF_DIV_MASK 0x03ff
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# define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
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# define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
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#define RADEON_P2PLL_DIV_0 0x002c
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# define RADEON_P2PLL_FB0_DIV_MASK 0x07ff
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# define RADEON_P2PLL_POST0_DIV_MASK 0x00070000
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#define RADEON_PIXCLKS_CNTL 0x0002d
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# define RADEON_PIX2CLK_SRC_SEL_MASK (3 << 0)
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# define RADEON_PIX2CLK_SRC_SEL_CPU_CLK (0 << 0)
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# define RADEON_PIX2CLK_SRC_SEL_PSCAN_CLK (1 << 0)
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# define RADEON_PIX2CLK_SRC_SEL_P2PLL_CLK (3 << 0)
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# define RADEON_PIXCLK_TV_SRC_SEL_MASK (1 << 8)
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# define RADEON_PIXCLK_TV_SRC_SEL_PIXCLK (0 << 8)
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# define RADEON_PIXCLK_TV_SRC_SEL_PIX2CLK (1 << 8)
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#define RADEON_HTOTAL2_CNTL 0x002e
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// r300: to be called after each CLOCK_CNTL_INDEX access;
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// all functions declared in this header take care of that
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// (hardware bug fix suggested by XFree86)
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void R300_PLLFix( accelerator_info *ai );
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// in general:
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// - the PLL is connected via special port
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// - you need first to choose the PLL register and then write/read its value
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//
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// if atomic updates are not safe we:
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// - verify each time whether the right register is chosen
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// - verify all values written to PLL-registers
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// read value "val" from PLL-register "addr"
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uint32 Radeon_INPLL( accelerator_info *ai, int addr );
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// write value "val" to PLL-register "addr"
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void Radeon_OUTPLL( accelerator_info *ai, uint8 addr, uint32 val );
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// write "val" to PLL-register "addr" keeping bits "mask"
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void Radeon_OUTPLLP( accelerator_info *ai, uint8 addr, uint32 val, uint32 mask );
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#endif
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