57 lines
2.1 KiB
C
57 lines
2.1 KiB
C
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/*
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Copyright (c) 2002, Thomas Kurschel
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Part of Radeon driver
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Config registers (most are in PCI configuration space)
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*/
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#ifndef _CONFIG_REGS_H
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#define _CONFIG_REGS_H
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// mmio registers
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#define RADEON_CONFIG_CNTL 0x00e0
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#define RADEON_CONFIG_MEMSIZE 0x00f8
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# define RADEON_CONFIG_MEMSIZE_MASK 0x1ff00000
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// following registers can be accessed via PCI configuration space too
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// (PCI-configuration-space-add + 0xf00 = MMIO-address)
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#define RADEON_VENDOR_ID 0x0f00
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#define RADEON_DEVICE_ID 0x0f02
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#define RADEON_COMMAND 0x0f04
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#define RADEON_STATUS 0x0f06
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#define RADEON_REVISION_ID 0x0f08
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#define RADEON_REGPROG_INF 0x0f09
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#define RADEON_SUB_CLASS 0x0f0a
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#define RADEON_BASE_CODE 0x0f0b
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#define RADEON_CACHE_LINE 0x0f0c
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#define RADEON_LATENCY 0x0f0d
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#define RADEON_HEADER 0x0f0e
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#define RADEON_BIST 0x0f0f
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#define RADEON_MEM_BASE 0x0f10
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#define RADEON_IO_BASE 0x0f14
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#define RADEON_REG_BASE 0x0f18
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#define RADEON_ADAPTER_ID 0x0f2c //mirror of AADPER_ID_W
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#define RADEON_BIOS_ROM 0x0f30
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#define RADEON_CAPABILITIES_PTR 0x0f34
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#define RADEON_INTERRUPT_LINE 0x0f3c
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#define RADEON_INTERRUPT_PIN 0x0f3d
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#define RADEON_MIN_GRANT 0x0f3e
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#define RADEON_MAX_LATENCY 0x0f3f
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#define RADEON_ADAPTER_ID_W 0x0f4c
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#define RADEON_CAPABILITIES_ID 0x0f50
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#define RADEON_PMI_CAP_ID 0x0f50
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#define RADEON_PMI_NXT_CAP_PTR 0x0f51
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#define RADEON_PMI_PMC_REG 0x0f52
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#define RADEON_PMI_STATUS 0x0f54
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#define RADEON_PMI_DATA 0x0f57
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#define RADEON_AGP_CAP_ID 0x0f58
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#define RADEON_AGP_STATUS 0x0f5c
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#define RADEON_AGP_COMMAND 0x0f60
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#endif
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