2004-03-15 03:58:12 +03:00
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/*
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Copyright (c) 2002, Thomas Kurschel
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Part of Radeon driver
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BusMemory Control registers
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*/
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#ifndef _MEMCNTRL_REGS_H
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#define _MEMCNTRL_REGS_H
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#define RADEON_AGP_BASE 0x0170
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#define RADEON_MEM_CNTL 0x0140
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2007-03-01 12:00:49 +03:00
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# define RADEON_MEM_NUM_CHANNELS_MASK 0x01
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# define RADEON_MEM_USE_B_CH_ONLY (1<<1)
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# define RV100_HALF_MODE (1<<3)
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# define R300_MEM_NUM_CHANNELS_MASK 0x03
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# define R300_MEM_USE_CD_CH_ONLY (1<<2)
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2004-03-15 03:58:12 +03:00
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#define RADEON_MC_AGP_LOCATION 0x014c
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#define RADEON_MC_FB_LOCATION 0x0148
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#define RADEON_MEM_INIT_LAT_TIMER 0x0154
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#define RADEON_MEM_SDRAM_MODE_REG 0x0158
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# define RADEON_MEM_CFG_TYPE_MASK (1 << 30)
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# define RADEON_MEM_CFG_SDR (0 << 30)
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# define RADEON_MEM_CFG_DDR (1 << 30)
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2007-03-01 12:00:49 +03:00
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#define RADEON_NB_TOM 0x015c
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2004-07-16 04:46:01 +04:00
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#define RADEON_DISPLAY_BASE_ADDRESS 0x023c
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#define RADEON_CRTC2_DISPLAY_BASE_ADDRESS 0x033c
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#define RADEON_OV0_BASE_ADDRESS 0x043c
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2004-03-15 03:58:12 +03:00
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2005-04-01 18:16:38 +04:00
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#define RADEON_GRPH_BUFFER_CNTL 0x02f0
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# define RADEON_GRPH_START_REQ_MASK (0x7f)
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# define RADEON_GRPH_START_REQ_SHIFT 0
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# define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8)
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# define RADEON_GRPH_STOP_REQ_SHIFT 8
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# define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16)
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# define RADEON_GRPH_CRITICAL_POINT_SHIFT 16
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# define RADEON_GRPH_CRITICAL_CNTL (1<<28)
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# define RADEON_GRPH_BUFFER_SIZE (1<<29)
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# define RADEON_GRPH_CRITICAL_AT_SOF (1<<30)
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# define RADEON_GRPH_STOP_CNTL (1<<31)
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#define RADEON_GRPH2_BUFFER_CNTL 0x03f0
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# define RADEON_GRPH2_START_REQ_MASK (0x7f)
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# define RADEON_GRPH2_START_REQ_SHIFT 0
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# define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8)
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# define RADEON_GRPH2_STOP_REQ_SHIFT 8
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# define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16)
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# define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16
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# define RADEON_GRPH2_CRITICAL_CNTL (1<<28)
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# define RADEON_GRPH2_BUFFER_SIZE (1<<29)
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# define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30)
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# define RADEON_GRPH2_STOP_CNTL (1<<31)
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2004-03-15 03:58:12 +03:00
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#endif
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