437 lines
16 KiB
C
437 lines
16 KiB
C
/* $NetBSD: ttwogareg.h,v 1.1 2000/12/21 20:51:55 thorpej Exp $ */
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Register description for the Digital Equipment Corp. T2 Gate Array,
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* the CBUS->PCI bridge found in the Sable, Sable-Gamma, and Lynx.
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*
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* Note all CBUS registers on the Sable are located in the T2. The
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* T2 is located at address 3.8E00.0000.
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*/
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/*
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* CBUS address bias for the Sable-Gamma and Lynx (EV5)
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*/
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#define T2_GAMMA_CBUS_BIAS 0x8000000000UL
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extern bus_addr_t ttwoga_gamma_cbus_bias;
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#define REGVAL(r) (*(__volatile u_int64_t *) \
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ALPHA_PHYS_TO_K0SEG(ttwoga_gamma_cbus_bias + (r)))
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/*
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* Sable/T2 System Address Map. There is a 34-bit physical address space.
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*
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* 0.0000.0000 Physical memory (2G - cached)
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*
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* 0.8000.0000 Reserved (2G - cached)
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*
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* 1.0000.0000 Allocate invalid (2G - uncached)
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*
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* 1.8000.0000 PCI 1 Dense Memory (2G - uncached)
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*
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* 2.0000.0000 PCI 0 Sparse Memory (4G - uncached, 128M addressable)
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*
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* 3.0000.0000 PCI 1 Sparse Memory (2G - uncached, 64M addressable)
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*
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* 3.8000.0000 CBUS CSRs (256M - uncached)
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*
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* 3.9000.0000 PCI 0 Configuration (128M - uncached)
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*
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* 3.9800.0000 PCI 1 Configuration (128M - uncached)
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*
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* 3.a000.0000 PCI 0 Sparse I/O (256M - uncached, 8M addressable)
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*
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* 3.b000.0000 PCI 1 Sparse I/O (256M - uncached, 8M addressable)
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*
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* 3.c000.0000 PCI 0 Dense Memory (1G - uncached)
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*/
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#define T2_PCI1_DMEM_BASE 0x180000000UL
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#define T2_PCI0_SMEM_BASE 0x200000000UL
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#define T2_PCI1_SMEM_BASE 0x300000000UL
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#define T2_CBUS_BASE 0x380000000UL
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#define T2_PCI0_CONF_BASE 0x390000000UL
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#define T2_PCI1_CONF_BASE 0x398000000UL
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#define T2_PCI0_SIO_BASE 0x3a0000000UL
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#define T2_PCI1_SIO_BASE 0x3b0000000UL
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#define T2_PCI0_DMEM_BASE 0x3c0000000UL
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/*
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* CBUS address map:
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*
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* 3.8000.0000 CPU0 CSRs
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* 3.8100.0000 CPU1 CSRs
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* 3.8200.0000 CPU2 CSRs
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* 3.8300.0000 CPU3 CSRs
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* 3.8400.0000 reserved
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* 3.8700.0000 reserved
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* 3.8800.0000 MEM0 CSRs
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* 3.8900.0000 MEM1 CSRs
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* 3.8a00.0000 MEM2 CSRs
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* 3.8b00.0000 MEM3 CSRs
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* 3.8c00.0000 reserved
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* 3.8e00.0000 T2 Gate Array (PCI interface)
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* 3.8f00.0000 Expansion I/O
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*/
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#define T2_CBUS_SLOT_STRIDE 0x01000000UL
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#define T2_CBUS_CPUn_BASE(n) (T2_CBUS_BASE + 0x00000000UL + \
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((n) * T2_CBUS_SLOT_STRIDE))
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#if 0
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#define T2_CBUS_CPU0_BASE (T2_CBUS_BASE + 0x00000000UL)
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#define T2_CBUS_CPU1_BASE (T2_CBUS_BASE + 0x01000000UL)
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#define T2_CBUS_CPU2_BASE (T2_CBUS_BASE + 0x02000000UL)
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#define T2_CBUS_CPU3_BASE (T2_CBUS_BASE + 0x03000000UL)
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#endif
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#define T2_CBUS_MEMn_BASE(n) (T2_CBUS_BASE + 0x08000000UL + \
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((n) * T2_CBUS_SLOT_STRIDE))
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#if 0
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#define T2_CBUS_MEM0_BASE (T2_CBUS_BASE + 0x08000000UL)
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#define T2_CBUS_MEM1_BASE (T2_CBUS_BASE + 0x09000000UL)
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#define T2_CBUS_MEM2_BASE (T2_CBUS_BASE + 0x0a000000UL)
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#define T2_CBUS_MEM3_BASE (T2_CBUS_BASE + 0x0b000000UL)
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#endif
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#define T2_CBUS_TTWOGA_BASE (T2_CBUS_BASE + 0x0e000000UL)
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#define T2_CBUS_EXPIO_BASE (T2_CBUS_BASE + 0x0f000000UL)
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/*
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* CBUS CPU module control/status registers.
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*/
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#define T2_SABLE_BCC 0x00000000 /* Backup Cache Control */
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#define T2_SABLE_BCCE 0x00000020 /* Backup Cache Correctable Error */
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#define T2_SABLE_BCCEA 0x00000040 /* Backup Cache Correctable Error
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Address (latched) */
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#define T2_SABLE_BCUE 0x00000080 /* Backup Cache Uncorrectable Error */
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#define T2_SABLE_BCUEA 0x000000a0 /* Backup Cache Uncorrectable Error
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Address (latched) */
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#define T2_SABLE_DTER 0x000000c0 /* Duplicate Tag Error */
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#define T2_SABLE_CBCTL 0x000000e0 /* CBUS Control */
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#define T2_SABLE_CBE 0x00000100 /* CBUS Error */
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#define T2_SABLE_CBEAL 0x00000120 /* CBUS Error Address Low (latched) */
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#define T2_SABLE_CBEAH 0x00000140 /* CBUS Error Address High (latched) */
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#define T2_SABLE_PMBX 0x00000180 /* Processor Mailbox */
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#define T2_SABLE_IPIR 0x000001a0 /* Interprocessor Interrupt Request */
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#define T2_SABLE_SIC 0x000001c0 /* System Interrupt Clear */
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#define T2_SABLE_ADLK 0x000001e0 /* Address Lock */
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#define T2_SABLE_MADRL 0x00000200 /* CBUS Miss Address */
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#define T2_SABLE_REV 0x00000220 /* CMIC Revision */
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/*
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* T2 Gate Array control/status registers.
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*/
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#define T2_SIZE 0x4e0
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#define _T2GA(b, r) REGVAL((T2_CBUS_TTWOGA_BASE + (T2_SIZE * (b))) + (r))
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#define T2GA(tcp, r) _T2GA((tcp)->tc_hose, (r))
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#define T2_IOCSR 0x0000UL /* I/O control status */
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/* 0x0000000000000001UL must be zero */
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#define IOCSR_EL 0x0000000000000002UL /* enable loopback */
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#define IOCSR_ESMV 0x0000000000000004UL /* enable state mach. vis. */
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#define IOCSR_PDBP 0x0000000000000008UL /* PCI drive bad parity */
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#define IOCSR_PCIS0_1 0x0000000000000010UL /* PCI slot 0 present */
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#define IOCSR_PCIS0_2 0x0000000000000020UL /* PCI slot 0 present */
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#define IOCSR_PINT 0x0000000000000040UL /* PCI interrupt high */
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#define IOCSR_ENTLBEC 0x0000000000000080UL /* enable TLB error check */
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#define IOCSR_ENCCMDA 0x0000000000000100UL /* enable CXACK check */
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/* 0x0000000000000200UL must be zero */
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#define IOCSR_ENXXCHG 0x0000000000000400UL /* EV5 excl. exchage enable */
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/* 0x0000000000000800UL must be zero */
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#define IOCSR_CAWWP0 0x0000000000001000UL /* CBUS c/a wr. wrong parity */
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#define IOCSR_CAWWP2 0x0000000000002000UL /* CBUS c/a wr. wrong parity */
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#define IOCSR_DWWPE 0x0000000000004000UL /* CBUS d. wr. wrong parity e */
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#define IOCSR_PCIS2_2 0x0000000000008000UL /* PCI slot 2 present */
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#define IOCSR_PSERR 0x0000000000010000UL /* power supply error */
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#define IOCSR_MBA7 0x0000000000020000UL /* ext. MBA<7> asserted */
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#define IOCSR_PCIS1_1 0x0000000000040000UL /* PCI slot 1 present */
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#define IOCSR_PCIS1_2 0x0000000000080000UL /* PCI slot 1 present */
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#define IOCSR_PDWWP1 0x0000000000100000UL /* PCI DMA WWP HW1 */
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#define IOCSR_PDWWP0 0x0000000000200000UL /* PCI DMA WWP HW0 */
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#define IOCSR_PBR 0x0000000000400000UL /* PCI bus reset */
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#define IOCSR_PIR 0x0000000000800000UL /* PCI interface reset */
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#define IOCSR_ENCOI 0x0000000001000000UL /* en. ACK,CUCERR, o-o-s */
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#define IOCSR_EPMS 0x0000000002000000UL /* enable PCI mem space */
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#define IOCSR_ETLB 0x0000000004000000UL /* enable TLB */
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#define IOCSR_EACC 0x0000000008000000UL /* en. atomic CBUS cycles */
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#define IOCSR_FTLB 0x0000000010000000UL /* flush TLB */
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#define IOCSR_ECPC 0x0000000020000000UL /* en. CBUS parity check */
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#define IOCSR_CIR 0x0000000040000000UL /* CBUS interface reset */
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#define IOCSR_EPL 0x0000000080000000UL /* enable PCI lock */
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#define IOCSR_CBBCE 0x0000000100000000UL /* CBUS bk-to-bk cycle en. */
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#define IOCSR_TRN 0x0000000e00000000UL /* T2 revision number */
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#define IOCSR_TRN_SHIFT 33
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#define TRN_T3 4
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#define IOCSR_SMVL 0x0000007000000000UL /* mach. state vis. select */
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#define IOCSR_SMVL_SHIFT 36
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#define SMVL_CBUS_CC 0 /* CBUS cycle counter */
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#define SMVL_CBUS_RES 1 /* CBUS responder */
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#define SMVL_CBUS_COM 2 /* CBUS commander */
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#define SMVL_PCI_COM 3 /* PCI commander */
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#define SMVL_PCI_RES 4 /* PCI responder */
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#define SMVL_TLB_INV 5 /* TLB invalidate */
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#define SMVL_PCI_COR 6 /* PCI corner */
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#define SMVL_CBUS_COR 7 /* CBUS corner */
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#define IOCSR_PCIS2_2H 0x0000008000000000UL /* PCI slot 2 present */
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#define IOCSR_EPR 0x0000010000000000UL /* enable passive release */
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/* 0x00000e0000000000UL must be zero */
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#define IOCSR_CAWWP1 0x0000100000000000UL /* CBUS c/a wr. wrong parity */
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#define IOCSR_CAWWP3 0x0000200000000000UL /* CBUS c/a wr. wrong parity */
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#define IOCSR_DWWPO 0x0000400000000000UL /* CBUS data wr. parity odd */
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/* 0x000f800000000000UL must be zero */
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#define IOCSR_PRM 0x0010000000000000UL /* PCI read multiple */
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#define IOCSR_PWM 0x0020000000000000UL /* PCI write multiple */
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#define IOCSR_FPRDPED 0x0040000000000000UL /* force PCI RDPE detect */
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#define IOCSR_FPADPED 0x0080000000000000UL /* force PCI APE detect */
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#define IOCSR_FPWDPED 0x0100000000000000UL /* force PCI WDPE detect */
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#define IOCSR_EPNMI 0x0200000000000000UL /* enable PCI NMI */
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#define IOCSR_EPDTI 0x0400000000000000UL /* enable PCI DTI */
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#define IOCSR_EPSEI 0x0800000000000000UL /* enable PCI SERR */
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#define IOCSR_EPPEI 0x1000000000000000UL /* enable PCI PERR */
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#define IOCSR_ERDPC 0x2000000000000000UL /* enable PCI RDP */
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#define IOCSR_EADPC 0x4000000000000000UL /* enable PCI AP int */
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#define IOCSR_EWDPC 0x8000000000000000UL /* enable PCI WDP */
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#define T2_CERR1 0x0020UL /* CBUS error 1 */
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#define CERR1_URE 0x0000000000000001UL /* uncorrectable read error */
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#define CERR1_NAE 0x0000000000000002UL /* no acknowledge */
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#define CERR1_CAPE 0x0000000000000004UL /* cmd addr. parity error */
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#define CERR1_MCAPE 0x0000000000000008UL /* missed cmd addr par err */
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#define CERR1_RWDPE 0x0000000000000010UL /* resp wr data par err */
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#define CERR1_MRWDPE 0x0000000000000020UL /* missed rsp data par err */
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#define CERR1_RDPE 0x0000000000000040UL /* read data par error */
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#define CERR1_MRDPE 0x0000000000000080UL /* missed read data per err */
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#define CERR1_CAPE0 0x0000000000000100UL /* CA par err LW 0 */
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#define CERR1_CAPE2 0x0000000000000200UL /* CA par err LW 2 */
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#define CERR1_DPE0 0x0000000000000400UL /* data par err LW 0 */
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#define CERR1_DPE2 0x0000000000000800UL /* data par err LW 2 */
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#define CERR1_DPE4 0x0000000000001000UL /* data par err LW 4 */
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#define CERR1_DPE6 0x0000000000002000UL /* data per err LW 6 */
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/* 0x000000000000c000UL must be zero */
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#define CERR1_CWDP 0x0000000000010000UL /* cmdr wr. data par err */
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#define CERR1_BSE 0x0000000000020000UL /* bus sync error */
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#define CERR1_IPFNE 0x0000000000040000UL /* invalid PFN */
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/* 0x000000fffff80000UL must be zero */
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#define CERR1_CAPE1 0x0000010000000000UL /* CA par err LW 1 */
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#define CERR1_CAPE3 0x0000020000000000UL /* CA par err LW 3 */
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#define CERR1_DPE1 0x0000040000000000UL /* data par err LW 1 */
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#define CERR1_DPE3 0x0000080000000000UL /* data par err LW 3 */
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#define CERR1_DPE5 0x0000100000000000UL /* data par err LW 5 */
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#define CERR1_DPE7 0x0000200000000000UL /* data par err LW 7 */
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/* 0xffffc00000000000UL must be zero */
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#define T2_CERR2 0x0040UL /* CBUS error 2 */
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/*
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* These bits correspond to CBUS CAD [63:00] during the
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* command/address transfer of the failing cycle.
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*/
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#define T2_CERR3 0x0060UL /* CBUS error 3 */
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/*
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* These bits correspond to CBUS CAD [127:64] during the
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* command/address transfer of the failing cycle.
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*/
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#define T2_PERR1 0x0080UL /* PCI error 1 */
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#define PERR1_PWDPE 0x0000000000000001UL /* wr. data par error */
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#define PERR1_PAPE 0x0000000000000002UL /* addr par error */
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#define PERR1_PRDPE 0x0000000000000004UL /* rd. data par error */
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#define PERR1_PPE 0x0000000000000008UL /* parity error */
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#define PERR1_PSE 0x0000000000000010UL /* system error */
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#define PERR1_PDTE 0x0000000000000020UL /* device timeout error */
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#define PERR1_NMI 0x0000000000000040UL /* non-maskable interrupt */
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#define T2_PERR2 0x00a0UL /* PCI error 2 */
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#define PERR2_PEA 0x00000000ffffffffUL /* error address */
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#define PERR2_PEC 0x0000001f00000000UL /* error command */
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#define PERR2_PEC_SHIFT 32
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#define T2_PSCR 0x00c0UL /* PCI special cycle */
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#define T2_HAE0_1 0x00e0UL /* High Address Extension 1 */
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#define HAE0_1_PUA1 0x000000000000001fUL
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/*
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* PCI Upper Address -- PCI_AD<31:27> when accessing the 128M
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* window of PCI0 Sparse Memory.
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*/
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#define T2_HAE0_2 0x0100UL /* High Address Extension 2 */
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#define HAE0_2_PUA2 0x00000000000001ffUL
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/*
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* PCI Upper Address -- PCI_AD<31:23> when accessing the 8M
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* window of PCI0 I/O space.
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*/
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#define T2_HBASE 0x0120UL /* PCI Hole Base */
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#define HBASE_PHEA 0x00000000000001ffUL /* hole end */
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/* 0x0000000000001e00UL must be zero */
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#define HBASE_PHE1 0x0000000000002000UL /* hole enable 1 */
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#define HBASE_PHE2 0x0000000000004000UL /* hole enable 2 */
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#define HBASE_PHSA 0x0000000000ff8000UL /* hole start */
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#define T2_WBASE1 0x0140UL /* Window Base 1 */
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#define WBASEx_PWEA 0x0000000000000fffUL /* window end */
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/* 0x000000000003f000UL must be zero */
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#define WBASEx_SGE 0x0000000000040000UL /* scatter/gather enable */
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#define WBASEx_PWE 0x0000000000080000UL /* PCI window enable */
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#define WBASEx_PWSA 0x00000000fff00000UL /* window start */
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#define WBASEx_PWxA_SHIFT 20
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#define T2_WMASK1 0x0160UL /* Window Mask 1 */
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#define WMASKx_PWM 0x000000007ff00000UL /* PCI window mask */
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#define T2_TBASE1 0x0180UL /* Translated Base 1 */
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#define TBASEx_TBA 0x000000007ffffe00UL /* translated base address */
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#define T2_WBASE2 0x01a0UL /* Window Base 2 */
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#define T2_WMASK2 0x01c0UL /* Window Mask 2 */
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#define T2_TBASE2 0x01e0UL /* Translated Base 2 */
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#define T2_TLBBR 0x0200UL /* TLB bypass */
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#define TLBBR_TLBBV 0x0000000000000001UL /* TLB bypass valid */
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#define TLBRR_TLBBD 0x000000000007fffeUL /* TLB bypass data */
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#define T2_IVRPR 0x0220UL /* IVR passive release */
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#define IVRPR_PRVECT 0x00000000000000ffUL /* passive release vector */
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#define T2_IVIAR 0x0220UL /* IVR interrupt address (pass 2) */
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#define IVIAR_IV 0x0003ffff00000000UL /* interrupt vector address */
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#define T2_HAE0_3 0x0240UL /* High Address Extension 3 (pass 2) */
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#define HAE0_3_PCA 0x00000000c0000000UL
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#define HAE0_3_PCA_SHIFT 30
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/*
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* PCI Configuration Address -- PCI_AD<1:0> when accessing
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* PCI configuration space, used to differentiate between
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* Type 0 and Type 1 cycles.
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*/
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#define T2_HAE0_4 0x0260UL /* High Address Extension 4 (pass 2) */
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#define HAE0_4_PUA1 0x0000000000000003UL
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/*
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* PCI Upper Address -- PCI_AD<31:30> when accessing the 1G
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* window of PCI0 Dense Memory.
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*/
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#define T2_WBASE3 0x0280UL /* Window Base 3 (T3/T4) */
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#define T2_WMASK3 0x02a0UL /* Window Mask 3 (T3/T4) */
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#define T2_TBASE3 0x02c0UL /* Translated Base 3 (T3/T4) */
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/* 0x02e0UL unused */
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#define T2_TDR0 0x0300UL /* TLB Data 0 */
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#define TDRx_TLBTD 0x000000003fffffffUL /* TLB entry tag */
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#define TDRx_TLBV 0x0000000100000000UL /* TLB entry valid */
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#define TDRx_TLBPFN 0x0003fffe00000000UL /* TLB entry data */
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#define T2_TDR1 0x0320UL /* TLB Data 1 */
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#define T2_TDR2 0x0340UL /* TLB Data 2 */
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#define T2_TDR3 0x0360UL /* TLB Data 3 */
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#define T2_TDR4 0x0380UL /* TLB Data 4 */
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#define T2_TDR5 0x03a0UL /* TLB Data 5 */
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#define T2_TDR6 0x03c0UL /* TLB Data 6 */
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#define T2_TDR7 0x03e0UL /* TLB Data 7 */
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#define T2_WBASE4 0x0400UL /* Window Base 4 (T3/T4) */
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#define T2_WMASK4 0x0420UL /* Window Mask 4 (T3/T4) */
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#define T2_TBASE4 0x0440UL /* Translated Base 4 (T3/T4) */
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#define T2_AIR 0x0460UL /* Address Indirection (T3/T4) */
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#define T2_VAR 0x0480UL /* Vector Address (T3/T4) */
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#define T2_DIR 0x04a0UL /* Data Indirection (T3/T4) */
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#define T2_ICE 0x04c0UL /* IC enable (T3/T4) */
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