4d9e9f6912
Both if_bge* and brgphy.[ch]:
Check the parent's MAC and use the quirk code for the bug like OpenBSD and
FreeBSD. Some bugs can't identify the PHY ID. For example, 5704 Ax has the
ADC bug, but 5704 A3 and 5704 B0 have the same PHY ID and revision. Add
BGE_PHY_CRC_BUG, BGE_PHY_ADC_BUG, BGE_PHY_5704_A0_BUG, BGE_PHY_JITTER_BUG,
BGE_PHY_ADJUST_TRIM and BGE_PHY_BER_BUG for this flag. Some of the DSP
patches are newly taken from OpenBSD and FreeBSD.
if_bge*:
Remove duplicated BGE_CHIPID_BCM5714_A0 entry in the known CHIPID table.
Fix obsolete comments.
brgphy.[ch]:
Add some PHY IDs.
TODO:
Add more three quirk code into bge and brgphy (the brgphy side's are
currently #if0'ed).
Add support for bnx into brgphy (currently #if0'ed)
230 lines
10 KiB
C
230 lines
10 KiB
C
/* $NetBSD: brgphyreg.h,v 1.4 2009/04/19 11:10:36 msaitoh Exp $ */
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/*
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* Copyright (c) 2000
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* Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* FreeBSD: src/sys/dev/mii/brgphyreg.h,v 1.1 2000/04/22 01:58:17 wpaul Exp
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*/
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#ifndef _DEV_MII_BRGPHYREG_H_
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#define _DEV_MII_BRGPHYREG_H_
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/*
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* Broadcom BCM5400 registers
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*/
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#define BRGPHY_MII_PHY_EXTCTL 0x10 /* PHY extended control */
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#define BRGPHY_PHY_EXTCTL_MAC_PHY 0x8000 /* 10BIT/GMI-interface */
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#define BRGPHY_PHY_EXTCTL_DIS_CROSS 0x4000 /* Disable MDI crossover */
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#define BRGPHY_PHY_EXTCTL_TX_DIS 0x2000 /* Tx output disable d*/
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#define BRGPHY_PHY_EXTCTL_INT_DIS 0x1000 /* Interrupts disabled */
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#define BRGPHY_PHY_EXTCTL_F_INT 0x0800 /* Force interrupt */
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#define BRGPHY_PHY_EXTCTL_BY_45 0x0400 /* Bypass 4B5B-Decoder */
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#define BRGPHY_PHY_EXTCTL_BY_SCR 0x0200 /* Bypass scrambler */
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#define BRGPHY_PHY_EXTCTL_BY_MLT3 0x0100 /* Bypass MLT3 encoder */
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#define BRGPHY_PHY_EXTCTL_BY_RXA 0x0080 /* Bypass RX alignment */
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#define BRGPHY_PHY_EXTCTL_RES_SCR 0x0040 /* Reset scrambler */
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#define BRGPHY_PHY_EXTCTL_EN_LTR 0x0020 /* Enable LED traffic mode */
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#define BRGPHY_PHY_EXTCTL_LED_ON 0x0010 /* Force LEDs on */
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#define BRGPHY_PHY_EXTCTL_LED_OFF 0x0008 /* Force LEDs off */
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#define BRGPHY_PHY_EXTCTL_EX_IPG 0x0004 /* Extended TX IPG mode */
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#define BRGPHY_PHY_EXTCTL_3_LED 0x0002 /* Three link LED mode */
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#define BRGPHY_PHY_EXTCTL_HIGH_LA 0x0001 /* GMII Fifo Elasticy (?) */
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#define BRGPHY_MII_PHY_EXTSTS 0x11 /* PHY extended status */
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#define BRGPHY_PHY_EXTSTS_CROSS_STAT 0x2000 /* MDI crossover status */
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#define BRGPHY_PHY_EXTSTS_INT_STAT 0x1000 /* Interrupt status */
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#define BRGPHY_PHY_EXTSTS_RRS 0x0800 /* Remote receiver status */
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#define BRGPHY_PHY_EXTSTS_LRS 0x0400 /* Local receiver status */
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#define BRGPHY_PHY_EXTSTS_LOCKED 0x0200 /* Locked */
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#define BRGPHY_PHY_EXTSTS_LS 0x0100 /* Link status */
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#define BRGPHY_PHY_EXTSTS_RF 0x0080 /* Remove fault */
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#define BRGPHY_PHY_EXTSTS_CE_ER 0x0040 /* Carrier ext error */
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#define BRGPHY_PHY_EXTSTS_BAD_SSD 0x0020 /* Bad SSD */
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#define BRGPHY_PHY_EXTSTS_BAD_ESD 0x0010 /* Bad ESS */
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#define BRGPHY_PHY_EXTSTS_RX_ER 0x0008 /* RX error */
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#define BRGPHY_PHY_EXTSTS_TX_ER 0x0004 /* TX error */
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#define BRGPHY_PHY_EXTSTS_LOCK_ER 0x0002 /* Lock error */
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#define BRGPHY_PHY_EXTSTS_MLT3_ER 0x0001 /* MLT3 code error */
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#define BRGPHY_MII_1000CTL 0x09 /* 1000baseT control */
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#define BRGPHY_1000CTL_TST 0xE000 /* Test modes */
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#define BRGPHY_1000CTL_MSE 0x1000 /* Master/Slave enable */
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#define BRGPHY_1000CTL_MSC 0x0800 /* Master/Slave configuration */
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#define BRGPHY_1000CTL_RD 0x0400 /* Repeater/DTE */
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#define BRGPHY_1000CTL_AFD 0x0200 /* Advertise full duplex */
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#define BRGPHY_1000CTL_AHD 0x0100 /* Advertise half duplex */
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#define BRGPHY_MII_RXERRCNT 0x12 /* RX error counter */
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#define BRGPHY_MII_FCERRCNT 0x13 /* false carrier sense counter */
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#define BGRPHY_FCERRCNT 0x00FF /* False carrier counter */
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#define BRGPHY_MII_RXNOCNT 0x14 /* RX not OK counter */
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#define BRGPHY_RXNOCNT_LOCAL 0xFF00 /* Local RX not OK counter */
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#define BRGPHY_RXNOCNT_REMOTE 0x00FF /* Local RX not OK counter */
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#define BRGPHY_MII_DSP_RW_PORT 0x15 /* DSP coefficient r/w port */
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#define BRGPHY_MII_EPHY_PTEST 0x17 /* 5906 PHY register */
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#define BRGPHY_MII_DSP_ADDR_REG 0x17 /* DSP coefficient addr register */
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#define BRGPHY_DSP_TAP_NUMBER_MASK 0x00
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#define BRGPHY_DSP_AGC_A 0x00
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#define BRGPHY_DSP_AGC_B 0x01
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#define BRGPHY_DSP_MSE_PAIR_STATUS 0x02
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#define BRGPHY_DSP_SOFT_DECISION 0x03
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#define BRGPHY_DSP_PHASE_REG 0x04
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#define BRGPHY_DSP_SKEW 0x05
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#define BRGPHY_DSP_POWER_SAVER_UPPER_BOUND 0x06
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#define BRGPHY_DSP_POWER_SAVER_LOWER_BOUND 0x07
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#define BRGPHY_DSP_LAST_ECHO 0x08
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#define BRGPHY_DSP_FREQUENCY 0x09
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#define BRGPHY_DSP_PLL_BANDWIDTH 0x0A
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#define BRGPHY_DSP_PLL_PHASE_OFFSET 0x0B
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#define BRGPHYDSP_FILTER_DCOFFSET 0x0C00
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#define BRGPHY_DSP_FILTER_FEXT3 0x0B00
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#define BRGPHY_DSP_FILTER_FEXT2 0x0A00
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#define BRGPHY_DSP_FILTER_FEXT1 0x0900
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#define BRGPHY_DSP_FILTER_FEXT0 0x0800
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#define BRGPHY_DSP_FILTER_NEXT3 0x0700
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#define BRGPHY_DSP_FILTER_NEXT2 0x0600
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#define BRGPHY_DSP_FILTER_NEXT1 0x0500
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#define BRGPHY_DSP_FILTER_NEXT0 0x0400
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#define BRGPHY_DSP_FILTER_ECHO 0x0300
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#define BRGPHY_DSP_FILTER_DFE 0x0200
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#define BRGPHY_DSP_FILTER_FFE 0x0100
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#define BRGPHY_DSP_CONTROL_ALL_FILTERS 0x1000
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#define BRGPHY_DSP_SEL_CH_0 0x0000
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#define BRGPHY_DSP_SEL_CH_1 0x2000
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#define BRGPHY_DSP_SEL_CH_2 0x4000
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#define BRGPHY_DSP_SEL_CH_3 0x6000
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#define BRGPHY_MII_AUXCTL 0x18 /* AUX control */
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#define BRGPHY_AUXCTL_LOW_SQ 0x8000 /* Low squelch */
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#define BRGPHY_AUXCTL_LONG_PKT 0x4000 /* RX long packets */
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#define BRGPHY_AUXCTL_ER_CTL 0x3000 /* Edgerate control */
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#define BRGPHY_AUXCTL_TX_TST 0x0400 /* TX test, always 1 */
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#define BRGPHY_AUXCTL_DIS_PRF 0x0080 /* dis part resp filter */
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#define BRGPHY_AUXCTL_DIAG_MODE 0x0004 /* Diagnostic mode */
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#define BRGPHY_MII_AUXSTS 0x19 /* AUX status */
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#define BRGPHY_AUXSTS_ACOMP 0x8000 /* autoneg complete */
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#define BRGPHY_AUXSTS_AN_ACK 0x4000 /* autoneg complete ack */
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#define BRGPHY_AUXSTS_AN_ACK_D 0x2000 /* autoneg complete ack detect */
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#define BRGPHY_AUXSTS_AN_NPW 0x1000 /* autoneg next page wait */
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#define BRGPHY_AUXSTS_AN_RES 0x0700 /* AN HDC */
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#define BRGPHY_AUXSTS_PDF 0x0080 /* Parallel detect. fault */
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#define BRGPHY_AUXSTS_RF 0x0040 /* remote fault */
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#define BRGPHY_AUXSTS_ANP_R 0x0020 /* AN page received */
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#define BRGPHY_AUXSTS_LP_ANAB 0x0010 /* LP AN ability */
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#define BRGPHY_AUXSTS_LP_NPAB 0x0008 /* LP Next page ability */
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#define BRGPHY_AUXSTS_LINK 0x0004 /* Link status */
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#define BRGPHY_AUXSTS_PRR 0x0002 /* Pause resolution-RX */
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#define BRGPHY_AUXSTS_PRT 0x0001 /* Pause resolution-TX */
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#define BRGPHY_RES_1000FD 0x0700 /* 1000baseT full duplex */
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#define BRGPHY_RES_1000HD 0x0600 /* 1000baseT half duplex */
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#define BRGPHY_RES_100FD 0x0500 /* 100baseT full duplex */
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#define BRGPHY_RES_100T4 0x0400 /* 100baseT4 */
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#define BRGPHY_RES_100HD 0x0300 /* 100baseT half duplex */
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#define BRGPHY_RES_10FD 0x0200 /* 10baseT full duplex */
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#define BRGPHY_RES_10HD 0x0100 /* 10baseT half duplex */
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#define BRGPHY_MII_ISR 0x1A /* interrupt status */
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#define BRGPHY_ISR_PSERR 0x4000 /* Pair swap error */
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#define BRGPHY_ISR_MDXI_SC 0x2000 /* MDIX Status Change */
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#define BRGPHY_ISR_HCT 0x1000 /* counter above 32K */
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#define BRGPHY_ISR_LCT 0x0800 /* all counter below 128 */
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#define BRGPHY_ISR_AN_PR 0x0400 /* Autoneg page received */
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#define BRGPHY_ISR_NO_HDCL 0x0200 /* No HCD Link */
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#define BRGPHY_ISR_NO_HDC 0x0100 /* No HCD */
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#define BRGPHY_ISR_USHDC 0x0080 /* Negotiated Unsupported HCD */
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#define BRGPHY_ISR_SCR_S_ERR 0x0040 /* Scrambler sync error */
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#define BRGPHY_ISR_RRS_CHG 0x0020 /* Remote RX status change */
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#define BRGPHY_ISR_LRS_CHG 0x0010 /* Local RX status change */
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#define BRGPHY_ISR_DUP_CHG 0x0008 /* Duplex mode change */
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#define BRGPHY_ISR_LSP_CHG 0x0004 /* Link speed changed */
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#define BRGPHY_ISR_LNK_CHG 0x0002 /* Link status change */
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#define BRGPHY_ISR_CRCERR 0x0001 /* CEC error */
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#define BRGPHY_MII_IMR 0x1B /* interrupt mask */
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#define BRGPHY_IMR_PSERR 0x4000 /* Pair swap error */
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#define BRGPHY_IMR_MDXI_SC 0x2000 /* MDIX Status Change */
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#define BRGPHY_IMR_HCT 0x1000 /* counter above 32K */
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#define BRGPHY_IMR_LCT 0x0800 /* all counter below 128 */
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#define BRGPHY_IMR_AN_PR 0x0400 /* Autoneg page received */
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#define BRGPHY_IMR_NO_HDCL 0x0200 /* No HCD Link */
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#define BRGPHY_IMR_NO_HDC 0x0100 /* No HCD */
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#define BRGPHY_IMR_USHDC 0x0080 /* Negotiated Unsupported HCD */
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#define BRGPHY_IMR_SCR_S_ERR 0x0040 /* Scrambler sync error */
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#define BRGPHY_IMR_RRS_CHG 0x0020 /* Remote RX status change */
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#define BRGPHY_IMR_LRS_CHG 0x0010 /* Local RX status change */
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#define BRGPHY_IMR_DUP_CHG 0x0008 /* Duplex mode change */
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#define BRGPHY_IMR_LSP_CHG 0x0004 /* Link speed changed */
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#define BRGPHY_IMR_LNK_CHG 0x0002 /* Link status change */
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#define BRGPHY_IMR_CRCERR 0x0001 /* CEC error */
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/*******************************************************/
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/* Begin: PHY register values for the 5706 PHY */
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/*******************************************************/
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/*
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* Shadow register 0x1C, bit 15 is write enable,
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* bits 14-10 select function (0x00 to 0x1F).
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*/
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#define BRGPHY_MII_SHADOW_1C 0x1C
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#define BRGPHY_SHADOW_1C_WRITE_EN 0x8000
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#define BRGPHY_SHADOW_1C_SELECT_MASK 0x7C00
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/* Shadow 0x1C Mode Control Register (select value 0x1F) */
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#define BRGPHY_SHADOW_1C_MODE_CTRL (0x1F << 10)
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/* When set, Regs 0-0x0F are 1000X, else 1000T */
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#define BRGPHY_SHADOW_1C_ENA_1000X 0x0001
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#define BRGPHY_TEST1 0x1E
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#define BRGPHY_TEST1_TRIM_EN 0x0010
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#define BRGPHY_TEST1_CRC_EN 0x8000
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#define BRGPHY_MII_TEST2 0x1F
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/*******************************************************/
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/* End: PHY register values for the 5706 PHY */
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/*******************************************************/
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#define BRGPHY_INTRS \
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~(BRGPHY_IMR_LNK_CHG|BRGPHY_IMR_LSP_CHG|BRGPHY_IMR_DUP_CHG)
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#endif /* _DEV_BRGPHY_MIIREG_H_ */
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