macallan 7add3da5f4 SuperSPARCs without cache controller need some extra cache flushs
With this a MULTIPROCESSOR kernel works again with a pair of SM50
2007-07-31 05:21:47 +00:00
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2007-07-30 18:20:08 +00:00
2007-07-30 23:28:13 +00:00