SuperSPARCs without cache controller need some extra cache flushs
With this a MULTIPROCESSOR kernel works again with a pair of SM50
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu.c,v 1.203 2007/05/28 21:24:17 mrg Exp $ */
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/* $NetBSD: cpu.c,v 1.204 2007/07/31 05:21:47 macallan Exp $ */
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/*
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* Copyright (c) 1996
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@ -52,7 +52,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.203 2007/05/28 21:24:17 mrg Exp $");
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__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.204 2007/07/31 05:21:47 macallan Exp $");
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#include "opt_multiprocessor.h"
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#include "opt_lockdebug.h"
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@ -1723,9 +1723,11 @@ static int mxcc = -1;
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else
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sc->flags |= CPUFLG_CACHEPAGETABLES;
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} else {
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sc->cache_flush = viking_cache_flush;
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#ifdef MULTIPROCESSOR
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if (sparc_ncpus > 1)
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sc->cache_flush = srmmu_cache_flush;
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#endif
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}
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/* Check all modules have the same MXCC configuration */
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if (mxcc != -1 && sc->mxcc != mxcc)
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panic("MXCC module mismatch");
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@ -1,4 +1,4 @@
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/* $NetBSD: iommu.c,v 1.86 2007/03/17 13:51:46 msaitoh Exp $ */
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/* $NetBSD: iommu.c,v 1.87 2007/07/31 05:21:47 macallan Exp $ */
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/*
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* Copyright (c) 1996
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@ -37,7 +37,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: iommu.c,v 1.86 2007/03/17 13:51:46 msaitoh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: iommu.c,v 1.87 2007/07/31 05:21:47 macallan Exp $");
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#include "opt_sparc_arch.h"
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@ -579,7 +579,8 @@ iommu_dmamap_load(bus_dma_tag_t t, bus_dmamap_t map,
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&dva, &sgsize)) != 0)
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return (error);
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if (sc->sc_cachecoherent == 0)
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if ((sc->sc_cachecoherent == 0) ||
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(curcpu()->cpu_type == CPUTYP_SS1_MBUS_NOMXCC))
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cache_flush(buf, buflen); /* XXX - move to bus_dma_sync? */
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/*
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