483 lines
14 KiB
C
483 lines
14 KiB
C
/* $NetBSD: dec_3min.c,v 1.40 2000/04/11 06:50:38 nisimura Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Jonathan Stone for
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* the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1988 University of Utah.
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department, The Mach Operating System project at
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* Carnegie-Mellon University and Ralph Campbell.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)machdep.c 8.3 (Berkeley) 1/12/94
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*/
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.40 2000/04/11 06:50:38 nisimura Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#include <machine/sysconf.h>
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#include <mips/mips/mips_mcclock.h> /* mcclock CPUspeed estimation */
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/* all these to get ioasic_base */
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#include <dev/tc/tcvar.h> /* tc type definitions for.. */
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#include <dev/tc/ioasicreg.h> /* ioasic interrrupt masks */
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#include <dev/tc/ioasicvar.h> /* ioasic_base */
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#include <pmax/pmax/machdep.h>
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#include <pmax/pmax/kmin.h> /* 3min baseboard addresses */
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#include <pmax/pmax/memc.h> /* 3min/maxine memory errors */
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#include <pmax/tc/sccvar.h>
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#include "rasterconsole.h"
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void dec_3min_init __P((void)); /* XXX */
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static void dec_3min_bus_reset __P((void));
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static void dec_3min_cons_init __P((void));
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static int dec_3min_intr __P((unsigned, unsigned, unsigned, unsigned));
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static void dec_3min_intr_establish __P((struct device *, void *,
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int, int (*)(void *), void *));
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static void kn02ba_wbflush __P((void));
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static unsigned kn02ba_clkread __P((void));
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/*
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* Local declarations.
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*/
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static u_int32_t kmin_tc3_imask;
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#ifdef MIPS3
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static unsigned latched_cycle_cnt;
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#endif
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void
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dec_3min_init()
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{
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int physmem_boardmax;
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platform.iobus = "tcbus";
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platform.bus_reset = dec_3min_bus_reset;
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platform.cons_init = dec_3min_cons_init;
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platform.iointr = dec_3min_intr;
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platform.intr_establish = dec_3min_intr_establish;
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platform.memsize = memsize_scan;
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platform.clkread = kn02ba_clkread;
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/* clear any memory errors */
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*(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0;
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kn02ba_wbflush();
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ioasic_base = MIPS_PHYS_TO_KSEG1(KMIN_SYS_ASIC);
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/*
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* Since all the motherboard interrupts come through the
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* IOASIC, it has to be turned off for all the spls and
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* since we don't know what kinds of devices are in the
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* TURBOchannel option slots, just splhigh().
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*/
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splvec.splbio = MIPS_SPL_0_1_2_3;
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splvec.splnet = MIPS_SPL_0_1_2_3;
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splvec.spltty = MIPS_SPL_0_1_2_3;
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splvec.splimp = MIPS_SPL_0_1_2_3;
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splvec.splclock = MIPS_SPL_0_1_2_3;
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splvec.splstatclock = MIPS_SPL_0_1_2_3;
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/* enable posting of MIPS_INT_MASK_3 to CAUSE register */
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*(u_int32_t *)(ioasic_base + IOASIC_IMSK) = KMIN_INTR_CLOCK;
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/* calibrate cpu_mhz value */
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mc_cpuspeed(ioasic_base+IOASIC_SLOT_8_START, MIPS_INT_MASK_3);
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*(u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3;
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*(u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe;
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#if 0
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*(u_int32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4);
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*(u_int32_t *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6);
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*(u_int32_t *)(ioasic_base + IOASIC_CSR) = 0x00000f00;
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#endif
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/* sanitize interrupt mask */
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kmin_tc3_imask = (KMIN_INTR_CLOCK|KMIN_INTR_PSWARN|KMIN_INTR_TIMEOUT);
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*(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0;
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*(u_int32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask;
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/*
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* The kmin memory hardware seems to wrap memory addresses
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* with 4Mbyte SIMMs, which causes the physmem computation
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* to lose. Find out how big the SIMMS are and set
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* max_ physmem accordingly.
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* XXX Do MAXINEs lose the same way?
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*/
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physmem_boardmax = KMIN_PHYS_MEMORY_END + 1;
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if ((KMIN_MSR_SIZE_16Mb & *(int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_MSR))
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== 0)
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physmem_boardmax = physmem_boardmax >> 2;
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physmem_boardmax = MIPS_PHYS_TO_KSEG1(physmem_boardmax);
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sprintf(cpu_model, "DECstation 5000/1%d (3MIN)", cpu_mhz);
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}
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/*
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* Initalize the memory system and I/O buses.
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*/
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static void
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dec_3min_bus_reset()
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{
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/*
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* Reset interrupts, clear any errors from newconf probes
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*/
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*(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0;
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kn02ba_wbflush();
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*(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0;
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kn02ba_wbflush();
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}
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static void
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dec_3min_cons_init()
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{
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int kbd, crt, screen;
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extern int tcfb_cnattach __P((int)); /* XXX */
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kbd = crt = screen = 0;
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prom_findcons(&kbd, &crt, &screen);
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if (screen > 0) {
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#if NRASTERCONSOLE > 0
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if (tcfb_cnattach(crt) > 0) {
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scc_lk201_cnattach(ioasic_base, 0x180000);
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return;
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}
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#endif
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printf("No framebuffer device configured for slot %d: ", crt);
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printf("using serial console\n");
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}
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/*
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* Delay to allow PROM putchars to complete.
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* FIFO depth * character time,
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* character time = (1000000 / (defaultrate / 10))
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*/
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DELAY(160000000 / 9600); /* XXX */
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scc_cnattach(ioasic_base, 0x180000);
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}
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static void
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dec_3min_intr_establish(dev, cookie, level, handler, arg)
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struct device *dev;
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void *cookie;
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int level;
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int (*handler) __P((void *));
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void *arg;
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{
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unsigned mask;
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switch ((int)cookie) {
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/* slots 0-2 don't interrupt through the IOASIC. */
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case SYS_DEV_OPT0:
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mask = MIPS_INT_MASK_0;
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break;
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case SYS_DEV_OPT1:
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mask = MIPS_INT_MASK_1;
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break;
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case SYS_DEV_OPT2:
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mask = MIPS_INT_MASK_2;
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break;
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case SYS_DEV_SCSI:
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mask = (IOASIC_INTR_SCSI | IOASIC_INTR_SCSI_PTR_LOAD |
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IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E);
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break;
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case SYS_DEV_LANCE:
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mask = KMIN_INTR_LANCE;
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break;
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case SYS_DEV_SCC0:
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mask = KMIN_INTR_SCC_0;
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break;
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case SYS_DEV_SCC1:
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mask = KMIN_INTR_SCC_1;
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break;
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default:
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#ifdef DIAGNOSTIC
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printf("warning: enabling unknown intr %x\n", (int)cookie);
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#endif
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return;
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}
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#if defined(DEBUG)
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printf("3MIN: imask %x, enabling slot %d, dev %p handler %p\n",
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kmin_tc3_imask, (int)cookie, dev, handler);
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#endif
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/*
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* Enable the interrupt handler, and if it's an IOASIC
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* slot, set the IOASIC interrupt mask.
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* Otherwise, set the appropriate spl level in the R3000
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* register.
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* Be careful to set handlers before enabling, and disable
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* interrupts before clearing handlers.
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*/
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/* Set the interrupt handler and argument ... */
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intrtab[(int)cookie].ih_func = handler;
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intrtab[(int)cookie].ih_arg = arg;
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/* ... and set the relevant mask */
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switch ((int)cookie) {
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case SYS_DEV_OPT0:
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case SYS_DEV_OPT1:
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case SYS_DEV_OPT2:
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/* it's an option slot */
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{
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int s = splhigh();
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s |= mask;
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splx(s);
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}
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break;
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default:
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/* it's a baseboard device going via the IOASIC */
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kmin_tc3_imask |= mask;
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break;
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}
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*(u_int32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask;
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kn02ba_wbflush();
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}
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#define CHECKINTR(slot, bits) \
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do { \
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if (can_serve & (bits)) { \
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intrcnt[slot] += 1; \
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(*intrtab[slot].ih_func)(intrtab[slot].ih_arg); \
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} \
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} while (0)
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static int
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dec_3min_intr(status, cause, pc, ipending)
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unsigned status;
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unsigned cause;
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unsigned pc;
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unsigned ipending;
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{
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static int user_warned = 0;
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static int intr_depth = 0;
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u_int32_t old_mask;
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intr_depth++;
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old_mask = *(u_int32_t *)(ioasic_base + IOASIC_IMSK);
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if (ipending & MIPS_INT_MASK_4)
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prom_haltbutton();
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if (ipending & MIPS_INT_MASK_3) {
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/* NB: status & MIPS_INT_MASK3 must also be set */
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/* masked interrupts are still observable */
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u_int32_t intr, imsk, can_serve, turnoff;
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turnoff = 0;
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intr = *(u_int32_t *)(ioasic_base + IOASIC_INTR);
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imsk = *(u_int32_t *)(ioasic_base + IOASIC_IMSK);
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can_serve = intr & imsk;
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if (intr & IOASIC_INTR_SCSI_PTR_LOAD) {
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turnoff |= IOASIC_INTR_SCSI_PTR_LOAD;
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#ifdef notdef
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asc_dma_intr();
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#endif
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}
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if (intr & (IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E))
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turnoff |= IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E;
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if (intr & IOASIC_INTR_LANCE_READ_E)
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turnoff |= IOASIC_INTR_LANCE_READ_E;
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if (turnoff)
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*(u_int32_t *)(ioasic_base + IOASIC_INTR) = ~turnoff;
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if (intr & KMIN_INTR_TIMEOUT)
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kn02ba_errintr();
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if (intr & KMIN_INTR_CLOCK) {
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struct clockframe cf;
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__asm __volatile("lbu $0,48(%0)" ::
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"r"(ioasic_base + IOASIC_SLOT_8_START));
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#ifdef MIPS3
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if (CPUISMIPS3) {
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latched_cycle_cnt = mips3_cycle_count();
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}
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#endif
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cf.pc = pc;
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cf.sr = status;
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hardclock(&cf);
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intrcnt[HARDCLOCK]++;
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}
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/* If clock interrups were enabled, re-enable them ASAP. */
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if (old_mask & KMIN_INTR_CLOCK) {
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/* ioctl interrupt mask to splclock and higher */
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*(u_int32_t *)(ioasic_base + IOASIC_IMSK)
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= old_mask &
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~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 |
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IOASIC_INTR_LANCE|IOASIC_INTR_SCSI);
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kn02ba_wbflush();
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_splset(MIPS_SR_INT_IE | (status & MIPS_INT_MASK_3));
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}
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if (intr_depth > 1)
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goto done;
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CHECKINTR(SYS_DEV_SCC0, IOASIC_INTR_SCC_0);
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CHECKINTR(SYS_DEV_SCC1, IOASIC_INTR_SCC_1);
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#ifdef notyet /* untested */
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/* If tty interrupts were enabled, re-enable them ASAP. */
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if ((old_mask & (KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) ==
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(KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) {
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*imaskp = old_mask &
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~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 |
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IOASIC_INTR_LANCE|IOASIC_INTR_SCSI);
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kn02ba_wbflush();
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}
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/* XXX until we know about SPLs of TC options. */
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if (intr_depth > 1)
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goto done;
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#endif
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CHECKINTR(SYS_DEV_LANCE, IOASIC_INTR_LANCE);
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CHECKINTR(SYS_DEV_SCSI, IOASIC_INTR_SCSI);
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if (user_warned && ((intr & KMIN_INTR_PSWARN) == 0)) {
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printf("%s\n", "Power supply ok now.");
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user_warned = 0;
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}
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if ((intr & KMIN_INTR_PSWARN) && (user_warned < 3)) {
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user_warned++;
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printf("%s\n", "Power supply overheating");
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}
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}
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if ((ipending & MIPS_INT_MASK_0) && intrtab[SYS_DEV_OPT0].ih_func) {
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(*intrtab[SYS_DEV_OPT0].ih_func)(intrtab[SYS_DEV_OPT0].ih_arg);
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intrcnt[SYS_DEV_OPT0]++;
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}
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if ((ipending & MIPS_INT_MASK_1) && intrtab[SYS_DEV_OPT1].ih_func) {
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(*intrtab[SYS_DEV_OPT1].ih_func)(intrtab[SYS_DEV_OPT1].ih_arg);
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intrcnt[SYS_DEV_OPT1]++;
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}
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if ((ipending & MIPS_INT_MASK_2) && intrtab[SYS_DEV_OPT2].ih_func) {
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(*intrtab[SYS_DEV_OPT2].ih_func)(intrtab[SYS_DEV_OPT2].ih_arg);
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intrcnt[SYS_DEV_OPT2]++;
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}
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done:
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/* restore entry state */
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splhigh();
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intr_depth--;
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*(u_int32_t *)(ioasic_base + IOASIC_IMSK) = old_mask;
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return (MIPS_SR_INT_IE | (status & ~cause & MIPS_HARD_INT_MASK));
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}
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/*
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************************************************************************
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* Extra functions
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************************************************************************
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*/
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static void
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kn02ba_wbflush()
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{
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/* read twice IOASIC_IMSK */
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__asm __volatile("lw $0,%0; lw $0,%0" ::
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"i"(MIPS_PHYS_TO_KSEG1(KMIN_REG_IMSK)));
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}
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static unsigned
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kn02ba_clkread()
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{
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#ifdef MIPS3
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if (CPUISMIPS3) {
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u_int32_t mips3_cycles;
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mips3_cycles = mips3_cycle_count() - latched_cycle_cnt;
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/* XXX divides take 78 cycles: approximate with * 41/2048 */
|
|
return((mips3_cycles >> 6) + (mips3_cycles >> 8) +
|
|
(mips3_cycles >> 11));
|
|
}
|
|
#endif
|
|
return 0;
|
|
}
|