Forgot to remove mips_hardware_intr global variable.
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156e51244a
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@ -1,4 +1,4 @@
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/* $NetBSD: dec_3100.c,v 1.27 2000/04/11 02:43:54 nisimura Exp $ */
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/* $NetBSD: dec_3100.c,v 1.28 2000/04/11 06:50:37 nisimura Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
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@ -113,8 +113,6 @@ dec_3100_init()
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platform.memsize = memsize_scan;
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/* no high resolution timer available */
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mips_hardware_intr = dec_3100_intr;
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splvec.splbio = MIPS_SPL0;
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splvec.splnet = MIPS_SPL_0_1;
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splvec.spltty = MIPS_SPL_0_1_2;
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@ -1,4 +1,4 @@
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/* $NetBSD: dec_3max.c,v 1.29 2000/04/11 02:43:55 nisimura Exp $ */
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/* $NetBSD: dec_3max.c,v 1.30 2000/04/11 06:50:37 nisimura Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
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@ -73,7 +73,7 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: dec_3max.c,v 1.29 2000/04/11 02:43:55 nisimura Exp $");
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__KERNEL_RCSID(0, "$NetBSD: dec_3max.c,v 1.30 2000/04/11 06:50:37 nisimura Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -122,8 +122,6 @@ dec_3max_init()
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*(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR) = 0;
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kn02_wbflush();
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mips_hardware_intr = dec_3max_intr;
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splvec.splbio = MIPS_SPL0;
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splvec.splnet = MIPS_SPL0;
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splvec.spltty = MIPS_SPL0;
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@ -1,4 +1,4 @@
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/* $NetBSD: dec_3maxplus.c,v 1.38 2000/04/11 02:43:55 nisimura Exp $ */
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/* $NetBSD: dec_3maxplus.c,v 1.39 2000/04/11 06:50:37 nisimura Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
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@ -73,7 +73,7 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: dec_3maxplus.c,v 1.38 2000/04/11 02:43:55 nisimura Exp $");
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__KERNEL_RCSID(0, "$NetBSD: dec_3maxplus.c,v 1.39 2000/04/11 06:50:37 nisimura Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -132,8 +132,7 @@ dec_3maxplus_init()
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kn03_wbflush();
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ioasic_base = MIPS_PHYS_TO_KSEG1(KN03_SYS_ASIC);
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mips_hardware_intr = dec_3maxplus_intr;
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/*
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* 3MAX+ IOASIC interrupts come through INT 0, while
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* clock interrupt does via INT 1. splclock and splstatclock
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@ -1,4 +1,4 @@
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/* $NetBSD: dec_3min.c,v 1.39 2000/04/11 02:43:55 nisimura Exp $ */
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/* $NetBSD: dec_3min.c,v 1.40 2000/04/11 06:50:38 nisimura Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
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@ -73,7 +73,7 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.39 2000/04/11 02:43:55 nisimura Exp $");
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__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.40 2000/04/11 06:50:38 nisimura Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -136,7 +136,6 @@ dec_3min_init()
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kn02ba_wbflush();
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ioasic_base = MIPS_PHYS_TO_KSEG1(KMIN_SYS_ASIC);
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mips_hardware_intr = dec_3min_intr;
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/*
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* Since all the motherboard interrupts come through the
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@ -1,4 +1,4 @@
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/* $NetBSD: dec_5100.c,v 1.24 2000/04/11 02:43:56 nisimura Exp $ */
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/* $NetBSD: dec_5100.c,v 1.25 2000/04/11 06:50:38 nisimura Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
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@ -31,7 +31,7 @@
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*/
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: dec_5100.c,v 1.24 2000/04/11 02:43:56 nisimura Exp $");
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__KERNEL_RCSID(0, "$NetBSD: dec_5100.c,v 1.25 2000/04/11 06:50:38 nisimura Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -74,8 +74,6 @@ dec_5100_init()
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/* set correct wbflush routine for this motherboard */
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mips_set_wbflush(kn230_wbflush);
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mips_hardware_intr = dec_5100_intr;
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splvec.splbio = MIPS_SPL1;
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splvec.splnet = MIPS_SPL1;
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splvec.spltty = MIPS_SPL_0_1;
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@ -1,4 +1,4 @@
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/* $NetBSD: dec_maxine.c,v 1.30 2000/04/11 02:43:56 nisimura Exp $ */
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/* $NetBSD: dec_maxine.c,v 1.31 2000/04/11 06:50:38 nisimura Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
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@ -73,7 +73,7 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: dec_maxine.c,v 1.30 2000/04/11 02:43:56 nisimura Exp $");
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__KERNEL_RCSID(0, "$NetBSD: dec_maxine.c,v 1.31 2000/04/11 06:50:38 nisimura Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -132,7 +132,6 @@ dec_maxine_init()
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kn02ca_wbflush();
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ioasic_base = MIPS_PHYS_TO_KSEG1(XINE_SYS_ASIC);
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mips_hardware_intr = dec_maxine_intr;
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/*
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* MAXINE IOASIC interrupts come through INT 3, while
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