125 lines
4.6 KiB
C
125 lines
4.6 KiB
C
/* $NetBSD: iocreg.h,v 1.1 2003/12/15 10:23:52 sekiya Exp $ */
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/*
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* Copyright (c) 2003 Christopher Sekiya
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* Copyright (c) 2001 Rafal K. Boni
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARCH_SGIMIPS_IOC_IOCREG_H_
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#define _ARCH_SGIMIPS_IOC_IOCREG_H_
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/*
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* IOC1/2 memory map.
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*
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* The IOC1/2 is connected to the HPC#0, PBus channel 6, so these registers
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* are based from the external register window for PBus channel 6 on HPC#0.
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*
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*/
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#define IOC_PLP_REGS 0x00 /* Parallel port registers */
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#define IOC_PLP_REGS_SIZE 0x2c
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#define IOC_PLP_DATA 0x00 /* Data register */
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#define IOC_PLP_CTL 0x04 /* Control register */
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#define IOC_PLP_STAT 0x08 /* Status register */
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#define IOC_PLP_DMACTL 0x0c /* DMA control register */
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#define IOC_PLP_INTSTAT 0x10 /* Interrupt status register */
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#define IOC_PLP_INTMASK 0x14 /* Interrupt mask register */
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#define IOC_PLP_TIMER1 0x18 /* Timer 1 register */
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#define IOC_PLP_TIMER2 0x1c /* Timer 2 register */
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#define IOC_PLP_TIMER3 0x20 /* Timer 3 register */
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#define IOC_PLP_TIMER4 0x24 /* Timer 4 register */
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#define IOC_SERIAL_REGS 0x30 /* Serial port registers */
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#define IOC_SERIAL_REGS_SIZE 0x0c
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#define IOC_SERIAL_PORT1_CMD 0x00 /* Port 1 command transfer */
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#define IOC_SERIAL_PORT1_DATA 0x04 /* Port 1 data transfer */
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#define IOC_SERIAL_PORT2_CMD 0x08 /* Port 2 command transfer */
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#define IOC_SERIAL_PORT2_DATA 0x0c /* Port 2 data transfer */
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#define IOC_KB_REGS 0x40 /* Keyboard/mouse registers */
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#define IOC_KB_REGS_SIZE 0x08
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/* Miscellaneous registers */
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#define IOC_MISC_REGS 0x48 /* Misc. IOC regs */
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#define IOC_MISC_REGS_SIZE 0x34
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#define IOC_GCSEL 0x48 /* General select register */
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#define IOC_GCREG 0x4c /* General control register */
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#define IOC_PANEL 0x50 /* Front Panel register */
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#define IOC_PANEL_POWER_STATE 0x01
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#define IOC_PANEL_POWER_IRQ 0x02
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#define IOC_PANEL_VDOWN_IRQ 0x10
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#define IOC_PANEL_VDOWN_HOLD 0x20
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#define IOC_PANEL_VUP_IRQ 0x40
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#define IOC_PANEL_VUP_HOLD 0x80
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#define IOC_SYSID 0x58 /* System ID register */
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#define IOC_SYSID_SYSTYPE 0x01 /* 0: Sapphire, 1: Full House */
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#define IOC_SYSID_BOARDREV 0x1e
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#define IOC_SYSID_BOARDREV_SHIFT 1
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#define IOC_SYSID_CHIPREV 0xe0
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#define IOC_SYSID_CHIPREV_SHIFT 5
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#define IOC_READ 0x60 /* Read register */
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#define IOC_READ_SCSI0_POWER 0x10
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#define IOC_READ_SCSI1_POWER 0x20
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#define IOC_READ_ENET_POWER 0x40
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#define IOC_READ_ENET_LINK 0x80
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#define IOC_DMASEL 0x68 /* DMA select register */
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#define IOC_DMASEL_ISDN_B 0x01
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#define IOC_DMASEL_ISDN_A 0x02
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#define IOC_DMASEL_PARALLEL 0x04
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#define IOC_DMASEL_SERIAL_10MHZ 0x00
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#define IOC_DMASEL_SERIAL_6MHZ 0x10
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#define IOC_DMASEL_SERIAL_EXTERNAL 0x20
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#define IOC_RESET 0x70 /* Reset register */
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#define IOC_RESET_PARALLEL 0x01
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#define IOC_RESET_PCKBC 0x02
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#define IOC_RESET_EISA 0x04
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#define IOC_RESET_ISDN 0x08
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#define IOC_RESET_LED_GREEN 0x10
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#define IOC_RESET_LED_RED 0x20
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#define IOC_RESET_LED_ORANGE 0x40
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#define IOC_WRITE 0x78 /* Write register */
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#define IOC_WRITE_ENET_NTH 0x01
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#define IOC_WRITE_ENET_UTP 0x02
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#define IOC_WRITE_ENET_AUI 0x04
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#define IOC_WRITE_ENET_AUTO 0x08
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#define IOC_WRITE_PC_UART2 0x10
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#define IOC_WRITE_PC_UART1 0x20
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#define IOC_WRITE_MARGIN_LOW 0x40
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#define IOC_WRITE_MARGIN_HIGH 0x80
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#endif /* _ARCH_SGIMIPS_IOC_IOCREG_H_ */
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