f4b7e59662
register, to avoid the compiler reordering instructions out of critical sections. Should fix PR port-sparc/41372.
356 lines
11 KiB
C
356 lines
11 KiB
C
/* $NetBSD: psl.h,v 1.45 2009/05/16 17:16:12 martin Exp $ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)psl.h 8.1 (Berkeley) 6/11/93
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*/
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#ifndef PSR_IMPL
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/*
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* SPARC Process Status Register (in psl.h for hysterical raisins). This
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* doesn't exist on the V9.
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*
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* The picture in the Sun manuals looks like this:
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* 1 1
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* 31 28 27 24 23 20 19 14 3 2 11 8 7 6 5 4 0
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* +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+
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* | impl | ver | icc | reserved |E|E| pil |S|P|E| CWP |
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* | | |n z v c| |C|F| | |S|T| |
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* +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+
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*/
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#define PSR_IMPL 0xf0000000 /* implementation */
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#define PSR_VER 0x0f000000 /* version */
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#define PSR_ICC 0x00f00000 /* integer condition codes */
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#define PSR_N 0x00800000 /* negative */
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#define PSR_Z 0x00400000 /* zero */
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#define PSR_O 0x00200000 /* overflow */
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#define PSR_C 0x00100000 /* carry */
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#define PSR_EC 0x00002000 /* coprocessor enable */
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#define PSR_EF 0x00001000 /* FP enable */
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#define PSR_PIL 0x00000f00 /* interrupt level */
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#define PSR_S 0x00000080 /* supervisor (kernel) mode */
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#define PSR_PS 0x00000040 /* previous supervisor mode (traps) */
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#define PSR_ET 0x00000020 /* trap enable */
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#define PSR_CWP 0x0000001f /* current window pointer */
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#define PSR_BITS "\20\16EC\15EF\10S\7PS\6ET"
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/*
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* SPARC V9 CCR register
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*/
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#define ICC_C 0x01L
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#define ICC_V 0x02L
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#define ICC_Z 0x04L
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#define ICC_N 0x08L
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#define XCC_SHIFT 4
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#define XCC_C (ICC_C<<XCC_SHIFT)
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#define XCC_V (ICC_V<<XCC_SHIFT)
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#define XCC_Z (ICC_Z<<XCC_SHIFT)
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#define XCC_N (ICC_N<<XCC_SHIFT)
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/*
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* SPARC V9 PSTATE register (what replaces the PSR in V9)
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*
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* Here's the layout:
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*
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* 11 10 9 8 7 6 5 4 3 2 1 0
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* +------------------------------------------------------------+
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* | IG | MG | CLE | TLE | MM | RED | PEF | AM | PRIV | IE | AG |
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* +------------------------------------------------------------+
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*/
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#define PSTATE_IG 0x800 /* enable spitfire interrupt globals */
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#define PSTATE_MG 0x400 /* enable spitfire MMU globals */
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#define PSTATE_CLE 0x200 /* current little endian */
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#define PSTATE_TLE 0x100 /* traps little endian */
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#define PSTATE_MM 0x0c0 /* memory model */
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#define PSTATE_MM_TSO 0x000 /* total store order */
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#define PSTATE_MM_PSO 0x040 /* partial store order */
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#define PSTATE_MM_RMO 0x080 /* Relaxed memory order */
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#define PSTATE_RED 0x020 /* RED state */
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#define PSTATE_PEF 0x010 /* enable floating point */
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#define PSTATE_AM 0x008 /* 32-bit address masking */
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#define PSTATE_PRIV 0x004 /* privileged mode */
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#define PSTATE_IE 0x002 /* interrupt enable */
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#define PSTATE_AG 0x001 /* enable alternate globals */
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#define PSTATE_BITS "\20\14IG\13MG\12CLE\11TLE\10\7MM\6RED\5PEF\4AM\3PRIV\2IE\1AG"
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/*
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* 32-bit code requires TSO or at best PSO since that's what's supported on
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* SPARC V8 and earlier machines.
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*
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* 64-bit code sets the memory model in the ELF header.
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*
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* We're running kernel code in TSO for the moment so we don't need to worry
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* about possible memory barrier bugs.
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*/
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#ifdef __arch64__
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#define PSTATE_PROM (PSTATE_MM_TSO|PSTATE_PRIV)
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#define PSTATE_NUCLEUS (PSTATE_MM_TSO|PSTATE_PRIV|PSTATE_AG)
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#define PSTATE_KERN (PSTATE_MM_TSO|PSTATE_PRIV)
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#define PSTATE_INTR (PSTATE_KERN|PSTATE_IE)
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#define PSTATE_USER32 (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE)
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#define PSTATE_USER (PSTATE_MM_RMO|PSTATE_IE)
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#else
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#define PSTATE_PROM (PSTATE_MM_TSO|PSTATE_PRIV)
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#define PSTATE_NUCLEUS (PSTATE_MM_TSO|PSTATE_AM|PSTATE_PRIV|PSTATE_AG)
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#define PSTATE_KERN (PSTATE_MM_TSO|PSTATE_AM|PSTATE_PRIV)
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#define PSTATE_INTR (PSTATE_KERN|PSTATE_IE)
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#define PSTATE_USER32 (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE)
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#define PSTATE_USER (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE)
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#endif
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/*
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* SPARC V9 TSTATE register
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*
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* 39 32 31 24 23 18 17 8 7 5 4 0
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* +-----+-----+-----+--------+---+-----+
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* | CCR | ASI | - | PSTATE | - | CWP |
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* +-----+-----+-----+--------+---+-----+
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* */
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#define TSTATE_CWP 0x01f
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#define TSTATE_PSTATE 0x6ff00
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#define TSTATE_PSTATE_SHIFT 8
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#define TSTATE_ASI 0xff000000LL
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#define TSTATE_ASI_SHIFT 24
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#define TSTATE_CCR 0xff00000000LL
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#define TSTATE_CCR_SHIFT 32
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#define PSRCC_TO_TSTATE(x) (((int64_t)(x)&PSR_ICC)<<(TSTATE_CCR_SHIFT-19))
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#define TSTATECCR_TO_PSR(x) (((x)&TSTATE_CCR)>>(TSTATE_CCR_SHIFT-19))
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/*
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* These are here to simplify life.
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*/
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#define TSTATE_IG (PSTATE_IG<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_MG (PSTATE_MG<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_CLE (PSTATE_CLE<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_TLE (PSTATE_TLE<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_MM (PSTATE_MM<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_MM_TSO (PSTATE_MM_TSO<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_MM_PSO (PSTATE_MM_PSO<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_MM_RMO (PSTATE_MM_RMO<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_RED (PSTATE_RED<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_PEF (PSTATE_PEF<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_AM (PSTATE_AM<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_PRIV (PSTATE_PRIV<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_IE (PSTATE_IE<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_AG (PSTATE_AG<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_BITS "\20\14IG\13MG\12CLE\11TLE\10\7MM\6RED\5PEF\4AM\3PRIV\2IE\1AG"
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#define TSTATE_KERN ((TSTATE_KERN)<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_USER ((TSTATE_USER)<<TSTATE_PSTATE_SHIFT)
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/*
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* SPARC V9 VER version register.
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*
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* 63 48 47 32 31 24 23 16 15 8 7 5 4 0
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* +-------+------+------+-----+-------+---+--------+
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* | manuf | impl | mask | - | maxtl | - | maxwin |
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* +-------+------+------+-----+-------+---+--------+
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*
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*/
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#define VER_MANUF 0xffff000000000000LL
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#define VER_MANUF_SHIFT 48
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#define VER_IMPL 0x0000ffff00000000LL
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#define VER_IMPL_SHIFT 32
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#define VER_MASK 0x00000000ff000000LL
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#define VER_MASK_SHIFT 24
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#define VER_MAXTL 0x000000000000ff00LL
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#define VER_MAXTL_SHIFT 8
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#define VER_MAXWIN 0x000000000000001fLL
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/*
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* Here are a few things to help us transition between user and kernel mode:
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*/
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/* Memory models */
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#define KERN_MM PSTATE_MM_TSO
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#define USER_MM PSTATE_MM_RMO
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/*
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* Register window handlers. These point to generic routines that check the
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* stack pointer and then vector to the real handler. We could optimize this
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* if we could guarantee only 32-bit or 64-bit stacks.
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*/
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#define WSTATE_KERN 026
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#define WSTATE_USER 022
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#define CWP 0x01f
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/* 64-byte alignment -- this seems the best place to put this. */
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#define BLOCK_SIZE 64
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#define BLOCK_ALIGN 0x3f
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#if defined(_KERNEL) && !defined(_LOCORE)
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/*
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* GCC pseudo-functions for manipulating PSR (primarily PIL field).
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*/
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static __inline int
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getpsr(void)
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{
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int psr;
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__asm volatile("rd %%psr,%0" : "=r" (psr));
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return (psr);
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}
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static __inline int
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getmid(void)
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{
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int mid;
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__asm volatile("rd %%tbr,%0" : "=r" (mid));
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return ((mid >> 20) & 0x3);
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}
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static __inline void
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setpsr(int newpsr)
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{
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__asm volatile("wr %0,0,%%psr" : : "r" (newpsr) : "memory");
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__asm volatile("nop; nop; nop");
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}
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static __inline void
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spl0(void)
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{
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int psr, oldipl;
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/*
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* wrpsr xors two values: we choose old psr and old ipl here,
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* which gives us the same value as the old psr but with all
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* the old PIL bits turned off.
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*/
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__asm volatile("rd %%psr,%0" : "=r" (psr) : : "memory");
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oldipl = psr & PSR_PIL;
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__asm volatile("wr %0,%1,%%psr" : : "r" (psr), "r" (oldipl));
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/*
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* Three instructions must execute before we can depend
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* on the bits to be changed.
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*/
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__asm volatile("nop; nop; nop");
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}
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/*
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* PIL 1 through 14 can use this macro.
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* (spl0 and splhigh are special since they put all 0s or all 1s
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* into the ipl field.)
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*/
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#define _SPLSET(name, newipl) \
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static __inline void name(void) \
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{ \
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int psr; \
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__asm volatile("rd %%psr,%0" : "=r" (psr)); \
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psr &= ~PSR_PIL; \
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__asm volatile("wr %0,%1,%%psr" : : \
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"r" (psr), "n" ((newipl) << 8)); \
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__asm volatile("nop; nop; nop" : : : "memory"); \
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}
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_SPLSET(spllowerschedclock, IPL_SCHED)
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typedef uint8_t ipl_t;
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typedef struct {
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ipl_t _ipl;
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} ipl_cookie_t;
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static inline ipl_cookie_t
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makeiplcookie(ipl_t ipl)
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{
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return (ipl_cookie_t){._ipl = ipl};
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}
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/* Raise IPL and return previous value */
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static __inline int
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splraiseipl(ipl_cookie_t icookie)
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{
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int newipl = icookie._ipl;
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int psr, oldipl;
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__asm volatile("rd %%psr,%0" : "=r" (psr));
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oldipl = psr & PSR_PIL;
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newipl <<= 8;
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if (newipl <= oldipl)
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return (oldipl);
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psr = (psr & ~oldipl) | newipl;
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__asm volatile("wr %0,0,%%psr" : : "r" (psr));
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__asm volatile("nop; nop; nop" : : : "memory");
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return (oldipl);
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}
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#include <sys/spl.h>
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#define splausoft() splraiseipl(makeiplcookie(IPL_SOFTAUDIO))
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#define splfdsoft() splraiseipl(makeiplcookie(IPL_SOFTFDC))
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#define splfd() splraiseipl(makeiplcookie(IPL_FD))
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#define splts102() splraiseipl(makeiplcookie(IPL_TS102))
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#define splzs() splraiseipl(makeiplcookie(IPL_ZS))
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/* splx does not have a return value */
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static __inline void
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splx(int newipl)
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{
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int psr;
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__asm volatile("rd %%psr,%0" : "=r" (psr) : : "memory");
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__asm volatile("wr %0,%1,%%psr" : : \
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"r" (psr & ~PSR_PIL), "rn" (newipl));
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__asm volatile("nop; nop; nop");
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}
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#endif /* KERNEL && !_LOCORE */
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#endif /* PSR_IMPL */
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