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Add memory clobbers to the inline assembler modifying/testing the %psr 

register, to avoid the compiler reordering instructions out of critical
sections. Should fix PR port-sparc/41372.
This commit is contained in:
martin 2009-05-16 17:16:12 +00:00
parent f26d5a00cc
commit f4b7e59662
1 changed files with 6 additions and 6 deletions
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12
sys/arch/sparc/include/psl.h
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@ -1,4 +1,4 @@
/* $NetBSD: psl.h,v 1.44 2007/02/19 02:57:40 mrg Exp $ */
/* $NetBSD: psl.h,v 1.45 2009/05/16 17:16:12 martin Exp $ */
/*
* Copyright (c) 1992, 1993
@ -252,7 +252,7 @@ getmid(void)
static __inline void
setpsr(int newpsr)
{
__asm volatile("wr %0,0,%%psr" : : "r" (newpsr));
__asm volatile("wr %0,0,%%psr" : : "r" (newpsr) : "memory");
__asm volatile("nop; nop; nop");
}
@ -266,7 +266,7 @@ spl0(void)
* which gives us the same value as the old psr but with all
* the old PIL bits turned off.
*/
__asm volatile("rd %%psr,%0" : "=r" (psr));
__asm volatile("rd %%psr,%0" : "=r" (psr) : : "memory");
oldipl = psr & PSR_PIL;
__asm volatile("wr %0,%1,%%psr" : : "r" (psr), "r" (oldipl));
@ -290,7 +290,7 @@ static __inline void name(void) \
psr &= ~PSR_PIL; \
__asm volatile("wr %0,%1,%%psr" : : \
"r" (psr), "n" ((newipl) << 8)); \
__asm volatile("nop; nop; nop"); \
__asm volatile("nop; nop; nop" : : : "memory"); \
}
_SPLSET(spllowerschedclock, IPL_SCHED)
@ -324,7 +324,7 @@ splraiseipl(ipl_cookie_t icookie)
psr = (psr & ~oldipl) | newipl;
__asm volatile("wr %0,0,%%psr" : : "r" (psr));
__asm volatile("nop; nop; nop");
__asm volatile("nop; nop; nop" : : : "memory");
return (oldipl);
}
@ -345,7 +345,7 @@ splx(int newipl)
{
int psr;
__asm volatile("rd %%psr,%0" : "=r" (psr));
__asm volatile("rd %%psr,%0" : "=r" (psr) : : "memory");
__asm volatile("wr %0,%1,%%psr" : : \
"r" (psr & ~PSR_PIL), "rn" (newipl));
__asm volatile("nop; nop; nop");