03adf4aad1
(`SUNW,sabre') for now, and it doesn't really quite work there yet anyway. the bus space/dma code is cloned from the sbus driver. the IOMMU code also is cloned from the sbus code, but separated out into iommu.c so that we can share it with the sbus driver. hopefully, much of the bus space/dma code can also be re-shared with the sbus driver and the ebus driver but for now these copies will do. support for the real UltraSPARC PCI (`SUNW,psycho') is unwritten, though most of this code is shared with it. we can probe PCI config space and try to configue devices, but interrupts don't work yet...
125 lines
4.1 KiB
C
125 lines
4.1 KiB
C
/* $NetBSD: psychovar.h,v 1.1 1999/06/04 13:42:15 mrg Exp $ */
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/*
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* Copyright (c) 1999 Matthew R. Green
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _SPARC64_DEV_PSYCHOVAR_H_
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#define _SPARC64_DEV_PSYCHOVAR_H_
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/* per real PCI bus info */
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struct psycho_softc;
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struct psycho_pbm {
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/* link to mum */
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struct psycho_softc *pp_sc;
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/*
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* note that the sabre really only has one ranges property,
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* used for both simba a and simba b (but the ranges for
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* real psychos are the same for PCI A and PCI B anyway).
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*/
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struct psycho_registers *pp_regs;
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struct psycho_ranges *pp_range;
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struct psycho_interrupt_map *pp_intmap;
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struct psycho_interrupt_map_mask pp_intmapmask;
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/* counts of above */
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int pp_nregs;
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int pp_nrange;
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int pp_nintmap;
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/* chipset tag for this instance */
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pci_chipset_tag_t pp_pc;
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/* our tags */
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bus_space_tag_t pp_memt;
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bus_space_tag_t pp_iot;
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bus_dma_tag_t pp_dmat;
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int pp_flags;
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/* and pointers into the psycho regs for our bits */
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struct pci_ctl *pp_pcictl;
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struct strbuf_diag *pp_sb_diag;
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};
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/*
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* per-PCI bus on mainbus softc structure; one for sabre, or two
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* per pair of psycho's.
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*/
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struct psycho_softc {
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struct device sc_dev;
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/*
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* one sabre has two simba's. psycho's are separately attached,
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* with the `other' psycho_pbm allocated at the first's attach.
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*/
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struct psycho_pbm *sc_sabre;
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struct psycho_pbm *__sc_psycho_this;
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struct psycho_pbm *__sc_psycho_other;
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#define sc_simba_a __sc_psycho_this
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#define sc_simba_b __sc_psycho_other
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#define sc_psycho_this __sc_psycho_this
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#define sc_psycho_other __sc_psycho_other
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/*
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* PSYCHO register. we record the base physical address of these
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* also as it is the base of the entire PSYCHO
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*/
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struct psychoreg *sc_regs;
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paddr_t sc_basepaddr;
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/* our tags (from parent) */
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bus_space_tag_t sc_bustag;
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bus_dma_tag_t sc_dmatag;
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/* config space */
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bus_space_tag_t sc_configtag;
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paddr_t sc_configaddr;
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int sc_clockfreq;
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int sc_node; /* prom node */
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int sc_mode; /* (whatareya?) */
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#define PSYCHO_MODE_SABRE 1 /* i'm a sabre (yob) */
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#define PSYCHO_MODE_PSYCHO_A 2 /* i'm a psycho (w*nker) */
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#define PSYCHO_MODE_PSYCHO_B 3 /* i'm another psycho (w*nker) */
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struct iommu_state sc_is;
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};
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/* config space is per-psycho. mem/io/dma are per-pci bus */
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bus_dma_tag_t psycho_alloc_dma_tag __P((struct psycho_pbm *));
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bus_space_tag_t psycho_alloc_bus_tag __P((struct psycho_pbm *, int));
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#define psycho_alloc_config_tag(pp) psycho_alloc_bus_tag((pp), PCI_CONFIG_BUS_SPACE)
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#define psycho_alloc_mem_tag(pp) psycho_alloc_bus_tag((pp), PCI_MEMORY_BUS_SPACE)
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#define psycho_alloc_io_tag(pp) psycho_alloc_bus_tag((pp), PCI_IO_BUS_SPACE)
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int psycho_intr_map __P((pcitag_t, int, int, pci_intr_handle_t *));
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#endif /* _SPARC64_DEV_PSYCHOVAR_H_ */
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