03adf4aad1
(`SUNW,sabre') for now, and it doesn't really quite work there yet anyway. the bus space/dma code is cloned from the sbus driver. the IOMMU code also is cloned from the sbus code, but separated out into iommu.c so that we can share it with the sbus driver. hopefully, much of the bus space/dma code can also be re-shared with the sbus driver and the ebus driver but for now these copies will do. support for the real UltraSPARC PCI (`SUNW,psycho') is unwritten, though most of this code is shared with it. we can probe PCI config space and try to configue devices, but interrupts don't work yet...
75 lines
3.1 KiB
C
75 lines
3.1 KiB
C
/* $NetBSD: simbareg.h,v 1.1 1999/06/04 13:42:15 mrg Exp $ */
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/*
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* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Christopher G. Demetriou
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* for the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* from: NetBSD: ppbreg.h,v 1.2 1996/03/14 02:35:35 cgd Exp
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*/
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/*
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* PCI-PCI Bridge chip register definitions and macros.
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* Derived from information found in the ``PCI to PCI Bridge
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* Architecture Specification, Revision 1.0, April 5, 1994.''
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*
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* XXX much is missing.
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*/
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/*
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* Register offsets
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*/
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#define PPB_REG_BASE0 0x10 /* Base Addr Reg. 0 */
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#define PPB_REG_BASE1 0x14 /* Base Addr Reg. 1 */
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#define PPB_REG_BUSINFO 0x18 /* Bus information */
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#define PPB_REG_IOSTATUS 0x1c /* I/O base+lim & sec stat */
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#define PPB_REG_MEM 0x20 /* Memory base/limit */
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#define PPB_REG_PREFMEM 0x24 /* Pref Mem base/limit */
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#define PPB_REG_PREFBASE_HI32 0x28 /* Pref Mem base high bits */
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#define PPB_REG_PREFLIM_HI32 0x2c /* Pref Mem lim high bits */
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#define PPB_REG_IO_HI 0x30 /* I/O base+lim high bits */
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#define PPB_REG_BRIDGECONTROL PCI_INTERRUPT_REG /* bridge control register */
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/*
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* Macros to extract the contents of the "Bus Info" register.
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*/
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#define PPB_BUSINFO_PRIMARY(bir) \
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((bir >> 0) & 0xff)
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#define PPB_BUSINFO_SECONDARY(bir) \
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((bir >> 8) & 0xff)
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#define PPB_BUSINFO_SUBORDINATE(bir) \
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((bir >> 16) & 0xff)
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#define PPB_BUSINFO_SECLAT(bir) \
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((bir >> 24) & 0xff)
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/*
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* Routine to translate between secondary bus interrupt pin/device number and
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* primary bus interrupt pin number.
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*/
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#define PPB_INTERRUPT_SWIZZLE(pin, device) \
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((((pin) + (device) - 1) % 4) + 1)
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