thorpej 4e990d9ccb Overhaul of the ARM cache code. This is mostly a simplification ... pass. Rather than providing a whole slew of cache operations that aren't ever used, distill them down to some useful primitives: icache_sync_all Synchronize I-cache icache_sync_range Synchronize I-cache range dcache_wbinv_all Write-back and Invalidate D-cache dcache_wbinv_range Write-back and Invalidate D-cache range dcache_inv_range Invalidate D-cache range dcache_wb_range Write-back D-cache range idcache_wbinv_all Write-back and Invalidate D-cache, Invalidate I-cache idcache_wbinv_range Write-back and Invalidate D-cache, Invalidate I-cache range Note: This does not yet include an overhaul of the actual asm files that implement the primitives. Instead, we've provided a safe default for each CPU type, and the individual CPU types can now be optimized one at a time.		2002-01-25 19:19:22 +00:00
..
amps.c
ampsreg.h
asc.c
ascreg.h
ascvar.h
cosc.c
coscreg.h
coscvar.h
csa.c	Use <machine/intr.h>, not <machine/irqhandler.h>	2001-11-27 00:53:11 +00:00
csc.c
cscreg.h
cscvar.h
esc.c
escreg.h	Initial commit of the splitting off of arch/acorn32 from arch/arm32.	2001-10-05 22:27:40 +00:00
escvar.h
icside_io_asm.S
icside.c
icsidereg.h
if_ie.c
if_iereg.h
if_ne_pbus.c
if_ne_pbusreg.h
netslot.c
podulebus_io_asm.S
podulebus_io.c	Initial commit of the splitting off of arch/acorn32 from arch/arm32.	2001-10-05 22:27:40 +00:00
podulebus.c
podulebus.h
ptsc.c
ptscreg.h
ptscvar.h
rapide_io_asm.S
rapide.c
rapidereg.h	Initial commit of the splitting off of arch/acorn32 from arch/arm32.	2001-10-05 22:27:40 +00:00
sbic.c
sbicreg.h
sbicvar.h
sfas.c
sfasreg.h
sfasvar.h
simide_io_asm.S
simide.c
simidereg.h	Initial commit of the splitting off of arch/acorn32 from arch/arm32.	2001-10-05 22:27:40 +00:00