91 lines
3.5 KiB
C
91 lines
3.5 KiB
C
/* $NetBSD: tegra_cecreg.h,v 1.1 2015/08/01 21:20:11 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _ARM_TEGRA_CECREG_H
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#define _ARM_TEGRA_CECREG_H
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#define CEC_SW_CONTROL_REG 0x00
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#define CEC_SW_CONTROL_MODE __BIT(31)
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#define CEC_SW_CONTROL_FILTERED_RX_DATA_PIN __BIT(4)
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#define CEC_SW_CONTROL_RAW_INPUT_DATA_PIN __BIT(0)
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#define CEC_HW_CONTROL_REG 0x04
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#define CEC_HW_CONTROL_TX_RX_MODE __BIT(31)
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#define CEC_HW_CONTROL_FAST_SIM_MODE __BIT(30)
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#define CEC_HW_CONTROL_TX_NAK_MODE __BIT(24)
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#define CEC_HW_CONTROL_RX_NAK_MODE __BIT(16)
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#define CEC_HW_CONTROL_RX_SNOOP __BIT(15)
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#define CEC_HW_CONTROL_RX_LOGICAL_ADDRS __BITS(14,0)
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#define CEC_INPUT_FILTER_REG 0x08
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#define CEC_INPUT_FILTER_MODE __BIT(31)
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#define CEC_INPUT_FILTER_FIFO_LENGTH __BITS(5,0)
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#define CEC_SPARE_REG 0x0c
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#define CEC_TX_REGISTER_REG 0x10
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#define CEC_TX_REGISTER_RETRY_FRAME __BIT(17)
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#define CEC_TX_REGISTER_GENERATE_START_BIT __BIT(16)
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#define CEC_TX_REGISTER_ADDRESS_MODE __BIT(12)
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#define CEC_TX_REGISTER_EOM __BIT(8)
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#define CEC_TX_REGISTER_DATA __BITS(7,0)
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#define CEC_RX_REGISTER_REG 0x14
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#define CEC_RX_REGISTER_ACK __BIT(9)
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#define CEC_RX_REGISTER_EOM __BIT(8)
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#define CEC_RX_REGISTER_DATA __BITS(7,0)
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#define CEC_RX_TIMING_0_REG 0x18
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#define CEC_RX_TIMING_1_REG 0x1c
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#define CEC_RX_TIMING_2_REG 0x20
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#define CEC_TX_TIMING_0_REG 0x24
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#define CEC_TX_TIMING_1_REG 0x28
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#define CEC_TX_TIMING_2_REG 0x2c
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#define CEC_INT_STAT_REG 0x30
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#define CEC_INT_MASK_REG 0x34
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#define CEC_INT_FILTERED_RX_DATA_PIN_TRANSITION_L2H __BIT(14)
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#define CEC_INT_FILTERED_RX_DATA_PIN_TRANSITION_H2L __BIT(13)
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#define CEC_INT_RX_BUS_ERROR_DETECTED __BIT(12)
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#define CEC_INT_RX_BUS_ANOMALY_DETECTED __BIT(11)
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#define CEC_INT_RX_START_BIT_DETECTED __BIT(10)
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#define CEC_INT_RX_REGISTER_OVERRUN __BIT(9)
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#define CEC_INT_RX_REGISTER_FULL __BIT(8)
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#define CEC_INT_TX_FRAME_TRANSMITTED __BIT(5)
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#define CEC_INT_TX_BUS_ANOMALY_DETECTED __BIT(4)
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#define CEC_INT_TX_ARBITRATION_FAILED __BIT(3)
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#define CEC_INT_TX_FRAME_OR_BLOCK_NAKD __BIT(2)
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#define CEC_INT_TX_REGISTER_UNDERRUN __BIT(1)
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#define CEC_INT_TX_REGISTER_EMPTY __BIT(0)
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#define CEC_HW_DEBUG_RX_REG 0x38
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#define CEC_HW_DEBUG_TX_REG 0x3c
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#define CEC_HW_SPARE_0_REG 0x40
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#endif /* _ARM_TEGRA_CECREG_H */
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