Add driver for Tegra HDMI CEC controller.

This commit is contained in:
jmcneill 2015-08-01 21:20:11 +00:00
parent 72fc9317eb
commit ab82ac0e7d
8 changed files with 529 additions and 8 deletions

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@ -1,4 +1,4 @@
# $NetBSD: files.tegra,v 1.14 2015/05/30 13:25:55 jmcneill Exp $
# $NetBSD: files.tegra,v 1.15 2015/08/01 21:20:11 jmcneill Exp $
#
# Configuration info for NVIDIA Tegra ARM Peripherals
#
@ -111,6 +111,11 @@ device tegrahdmi: edid, ddc_read_edid, videomode
attach tegrahdmi at tegraio with tegra_hdmi
file arch/arm/nvidia/tegra_hdmi.c tegra_hdmi
# HDMI CEC
device tegracec: hdmicecbus
attach tegracec at tegraio with tegra_cec
file arch/arm/nvidia/tegra_cec.c tegra_cec
# Console parameters
defparam opt_tegra.h CONADDR
defparam opt_tegra.h CONSPEED

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@ -1,4 +1,4 @@
/* $NetBSD: tegra_car.c,v 1.25 2015/07/29 14:30:18 jmcneill Exp $ */
/* $NetBSD: tegra_car.c,v 1.26 2015/08/01 21:20:11 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
@ -29,7 +29,7 @@
#include "locators.h"
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: tegra_car.c,v 1.25 2015/07/29 14:30:18 jmcneill Exp $");
__KERNEL_RCSID(0, "$NetBSD: tegra_car.c,v 1.26 2015/08/01 21:20:11 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@ -684,6 +684,18 @@ tegra_car_periph_i2c_enable(u_int port, u_int rate)
return 0;
}
void
tegra_car_periph_cec_enable(void)
{
bus_space_tag_t bst;
bus_space_handle_t bsh;
tegra_car_get_bs(&bst, &bsh);
bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_CEC);
bus_space_write_4(bst, bsh, CAR_RST_DEV_W_CLR_REG, CAR_DEV_W_CEC);
}
void
tegra_car_hdmi_enable(u_int rate)
{

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@ -0,0 +1,408 @@
/* $NetBSD: tegra_cec.c,v 1.1 2015/08/01 21:20:11 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include "locators.h"
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: tegra_cec.c,v 1.1 2015/08/01 21:20:11 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
#include <sys/device.h>
#include <sys/intr.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/mutex.h>
#include <sys/condvar.h>
#include <sys/poll.h>
#include <sys/select.h>
#include <dev/hdmicec/hdmicecio.h>
#include <dev/hdmicec/hdmicec_if.h>
#include <arm/nvidia/tegra_var.h>
#include <arm/nvidia/tegra_pmcreg.h>
#include <arm/nvidia/tegra_cecreg.h>
#define CEC_VENDORID_NVIDIA 0x00044b
static int tegra_cec_match(device_t, cfdata_t, void *);
static void tegra_cec_attach(device_t, device_t, void *);
static int tegra_cec_intr(void *);
struct tegra_cec_softc {
device_t sc_dev;
bus_space_tag_t sc_bst;
bus_space_handle_t sc_bsh;
void *sc_ih;
kmutex_t sc_lock;
kcondvar_t sc_cv;
const char *sc_hdmidevname;
device_t sc_cecdev;
struct selinfo sc_selinfo;
uint8_t sc_rxbuf[16];
int sc_rxlen;
bool sc_rxdone;
uint8_t sc_txbuf[16];
int sc_txlen;
int sc_txcur;
int sc_txerr;
bool sc_txdone;
};
static void tegra_cec_reset(struct tegra_cec_softc *);
static int tegra_cec_open(void *, int);
static void tegra_cec_close(void *);
static int tegra_cec_ioctl(void *, u_long, void *, int, lwp_t *);
static int tegra_cec_send(void *, const uint8_t *, size_t);
static ssize_t tegra_cec_recv(void *, uint8_t *, size_t);
static int tegra_cec_poll(void *, int, lwp_t *);
static const struct hdmicec_hw_if tegra_cec_hw_if = {
.open = tegra_cec_open,
.close = tegra_cec_close,
.ioctl = tegra_cec_ioctl,
.send = tegra_cec_send,
.recv = tegra_cec_recv,
.poll = tegra_cec_poll,
};
CFATTACH_DECL_NEW(tegra_cec, sizeof(struct tegra_cec_softc),
tegra_cec_match, tegra_cec_attach, NULL, NULL);
#define CEC_READ(sc, reg) \
bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
#define CEC_WRITE(sc, reg, val) \
bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
#define CEC_SET_CLEAR(sc, reg, set, clr) \
tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr))
static int
tegra_cec_match(device_t parent, cfdata_t cf, void *aux)
{
return 1;
}
static void
tegra_cec_attach(device_t parent, device_t self, void *aux)
{
struct tegra_cec_softc * const sc = device_private(self);
struct tegraio_attach_args * const tio = aux;
const struct tegra_locators * const loc = &tio->tio_loc;
prop_dictionary_t prop = device_properties(self);
struct hdmicec_attach_args caa;
sc->sc_dev = self;
sc->sc_bst = tio->tio_bst;
bus_space_subregion(tio->tio_bst, tio->tio_bsh,
loc->loc_offset, loc->loc_size, &sc->sc_bsh);
mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM);
cv_init(&sc->sc_cv, "tegracec");
selinit(&sc->sc_selinfo);
aprint_naive("\n");
aprint_normal(": HDMI CEC\n");
sc->sc_ih = intr_establish(loc->loc_intr, IPL_VM, IST_LEVEL|IST_MPSAFE,
tegra_cec_intr, sc);
if (sc->sc_ih == NULL) {
aprint_error_dev(self, "couldn't establish interrupt %d\n",
loc->loc_intr);
return;
}
aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr);
prop_dictionary_get_cstring_nocopy(prop, "hdmi-device",
&sc->sc_hdmidevname);
tegra_car_periph_cec_enable();
CEC_WRITE(sc, CEC_SW_CONTROL_REG, 0);
CEC_WRITE(sc, CEC_INPUT_FILTER_REG, 0);
CEC_WRITE(sc, CEC_HW_CONTROL_REG, 0);
CEC_WRITE(sc, CEC_INT_MASK_REG, 0);
CEC_WRITE(sc, CEC_INT_STAT_REG, 0xffffffff);
memset(&caa, 0, sizeof(caa));
caa.priv = sc;
caa.hwif = &tegra_cec_hw_if;
sc->sc_cecdev = config_found(self, &caa, NULL);
}
static int
tegra_cec_intr(void *priv)
{
struct tegra_cec_softc * const sc = priv;
uint32_t val;
int handled = 0;
mutex_enter(&sc->sc_lock);
const uint32_t int_stat = CEC_READ(sc, CEC_INT_STAT_REG);
if (int_stat & CEC_INT_RX_REGISTER_FULL) {
val = CEC_READ(sc, CEC_RX_REGISTER_REG);
sc->sc_rxbuf[sc->sc_rxlen++] =
__SHIFTOUT(val, CEC_RX_REGISTER_DATA);
if ((val & CEC_RX_REGISTER_EOM) != 0 ||
sc->sc_rxlen == 16) {
CEC_SET_CLEAR(sc, CEC_INT_MASK_REG, 0,
CEC_INT_RX_REGISTER_FULL);
sc->sc_rxdone = true;
cv_broadcast(&sc->sc_cv);
selnotify(&sc->sc_selinfo, POLLIN|POLLRDNORM,
NOTE_SUBMIT);
}
CEC_WRITE(sc, CEC_INT_STAT_REG, CEC_INT_RX_REGISTER_FULL);
++handled;
}
if (int_stat & CEC_INT_TX_REGISTER_EMPTY) {
if (sc->sc_txcur < sc->sc_txlen) {
const uint8_t destination = sc->sc_txbuf[0] & 0xf;
val = __SHIFTIN(sc->sc_txbuf[sc->sc_txcur],
CEC_TX_REGISTER_DATA);
if (sc->sc_txcur == 0)
val |= CEC_TX_REGISTER_GENERATE_START_BIT;
if (sc->sc_txcur == sc->sc_txlen - 1)
val |= CEC_TX_REGISTER_EOM;
if (destination == 0xf)
val |= CEC_TX_REGISTER_ADDRESS_MODE;
CEC_WRITE(sc, CEC_TX_REGISTER_REG, val);
CEC_WRITE(sc, CEC_INT_STAT_REG,
CEC_INT_TX_REGISTER_EMPTY);
++sc->sc_txcur;
} else {
CEC_SET_CLEAR(sc, CEC_INT_MASK_REG, 0,
CEC_INT_TX_REGISTER_EMPTY);
}
++handled;
}
if (int_stat & CEC_INT_TX_FRAME_TRANSMITTED) {
CEC_SET_CLEAR(sc, CEC_INT_MASK_REG, 0,
CEC_INT_TX_FRAME_TRANSMITTED |
CEC_INT_TX_FRAME_OR_BLOCK_NAKD);
CEC_WRITE(sc, CEC_INT_STAT_REG, CEC_INT_TX_FRAME_TRANSMITTED);
if (int_stat & CEC_INT_TX_FRAME_OR_BLOCK_NAKD) {
CEC_WRITE(sc, CEC_INT_STAT_REG,
CEC_INT_TX_FRAME_OR_BLOCK_NAKD);
sc->sc_txerr = ECONNREFUSED;
tegra_cec_reset(sc);
}
sc->sc_txdone = true;
cv_broadcast(&sc->sc_cv);
++handled;
}
if (int_stat & CEC_INT_TX_REGISTER_UNDERRUN) {
tegra_cec_reset(sc);
cv_broadcast(&sc->sc_cv);
++handled;
}
mutex_exit(&sc->sc_lock);
return handled;
}
static void
tegra_cec_reset(struct tegra_cec_softc *sc)
{
uint32_t val;
KASSERT(mutex_owned(&sc->sc_lock));
val = CEC_READ(sc, CEC_HW_CONTROL_REG);
CEC_WRITE(sc, CEC_HW_CONTROL_REG, 0);
CEC_WRITE(sc, CEC_INT_STAT_REG, 0xffffffff);
CEC_WRITE(sc, CEC_HW_CONTROL_REG, val);
}
static int
tegra_cec_open(void *priv, int flag)
{
struct tegra_cec_softc * const sc = priv;
mutex_enter(&sc->sc_lock);
sc->sc_rxlen = 0;
sc->sc_rxdone = false;
CEC_WRITE(sc, CEC_INT_MASK_REG, CEC_INT_RX_REGISTER_FULL);
CEC_WRITE(sc, CEC_HW_CONTROL_REG, CEC_HW_CONTROL_TX_RX_MODE);
mutex_exit(&sc->sc_lock);
return 0;
}
static void
tegra_cec_close(void *priv)
{
struct tegra_cec_softc * const sc = priv;
mutex_enter(&sc->sc_lock);
CEC_WRITE(sc, CEC_HW_CONTROL_REG, 0);
CEC_WRITE(sc, CEC_INT_MASK_REG, 0);
CEC_WRITE(sc, CEC_INT_STAT_REG, 0xffffffff);
mutex_exit(&sc->sc_lock);
}
static int
tegra_cec_get_phys_addr(struct tegra_cec_softc *sc, uint16_t *phys_addr)
{
device_t hdmidev;
if (sc->sc_hdmidevname == NULL)
return EIO;
hdmidev = device_find_by_xname(sc->sc_hdmidevname);
if (hdmidev == NULL)
return ENXIO;
const prop_dictionary_t prop = device_properties(hdmidev);
if (!prop_dictionary_get_uint16(prop, "physical-address", phys_addr))
return ENOTCONN;
return 0;
}
static int
tegra_cec_ioctl(void *priv, u_long cmd, void *data, int flag, lwp_t *l)
{
struct tegra_cec_softc * const sc = priv;
uint32_t val;
switch (cmd) {
case CEC_GET_PHYS_ADDR:
return tegra_cec_get_phys_addr(sc, data);
case CEC_GET_LOG_ADDRS:
val = CEC_READ(sc, CEC_HW_CONTROL_REG);
*(uint16_t *)data =
__SHIFTOUT(val, CEC_HW_CONTROL_RX_LOGICAL_ADDRS);
return 0;
case CEC_SET_LOG_ADDRS:
val = *(uint16_t *)data & 0x7fff;
CEC_SET_CLEAR(sc, CEC_HW_CONTROL_REG,
__SHIFTIN(val, CEC_HW_CONTROL_RX_LOGICAL_ADDRS),
CEC_HW_CONTROL_RX_LOGICAL_ADDRS);
return 0;
case CEC_GET_VENDOR_ID:
*(uint32_t *)data = CEC_VENDORID_NVIDIA;
return 0;
default:
return EINVAL;
}
}
static int
tegra_cec_send(void *priv, const uint8_t *data, size_t len)
{
struct tegra_cec_softc * const sc = priv;
int error = 0;
mutex_enter(&sc->sc_lock);
sc->sc_txdone = false;
sc->sc_txcur = 0;
sc->sc_txerr = 0;
memcpy(sc->sc_txbuf, data, len);
sc->sc_txlen = len;
CEC_SET_CLEAR(sc, CEC_INT_MASK_REG,
CEC_INT_TX_REGISTER_EMPTY |
CEC_INT_TX_FRAME_TRANSMITTED |
CEC_INT_TX_FRAME_OR_BLOCK_NAKD, 0);
while (sc->sc_txdone == false) {
error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_lock, hz);
if (error)
break;
}
if (sc->sc_txdone)
error = sc->sc_txerr;
mutex_exit(&sc->sc_lock);
return error;
}
static ssize_t
tegra_cec_recv(void *priv, uint8_t *data, size_t len)
{
struct tegra_cec_softc * const sc = priv;
ssize_t alen = -1;
int error = 0;
mutex_enter(&sc->sc_lock);
while (sc->sc_rxdone == false) {
error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_lock, hz);
if (error)
break;
}
if (sc->sc_rxdone) {
memcpy(data, sc->sc_rxbuf, sc->sc_rxlen);
alen = sc->sc_rxlen;
sc->sc_rxlen = 0;
sc->sc_rxdone = false;
}
mutex_exit(&sc->sc_lock);
return alen;
}
static int
tegra_cec_poll(void *priv, int events, lwp_t *l)
{
struct tegra_cec_softc * const sc = priv;
int revents;
revents = events & (POLLOUT | POLLWRNORM);
if ((events & (POLLIN | POLLRDNORM)) == 0)
return revents;
mutex_enter(&sc->sc_lock);
if (sc->sc_rxdone) {
revents = (events & (POLLIN | POLLRDNORM));
} else {
selrecord(l, &sc->sc_selinfo);
revents = 0;
}
mutex_exit(&sc->sc_lock);
return revents;
}

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@ -0,0 +1,90 @@
/* $NetBSD: tegra_cecreg.h,v 1.1 2015/08/01 21:20:11 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _ARM_TEGRA_CECREG_H
#define _ARM_TEGRA_CECREG_H
#define CEC_SW_CONTROL_REG 0x00
#define CEC_SW_CONTROL_MODE __BIT(31)
#define CEC_SW_CONTROL_FILTERED_RX_DATA_PIN __BIT(4)
#define CEC_SW_CONTROL_RAW_INPUT_DATA_PIN __BIT(0)
#define CEC_HW_CONTROL_REG 0x04
#define CEC_HW_CONTROL_TX_RX_MODE __BIT(31)
#define CEC_HW_CONTROL_FAST_SIM_MODE __BIT(30)
#define CEC_HW_CONTROL_TX_NAK_MODE __BIT(24)
#define CEC_HW_CONTROL_RX_NAK_MODE __BIT(16)
#define CEC_HW_CONTROL_RX_SNOOP __BIT(15)
#define CEC_HW_CONTROL_RX_LOGICAL_ADDRS __BITS(14,0)
#define CEC_INPUT_FILTER_REG 0x08
#define CEC_INPUT_FILTER_MODE __BIT(31)
#define CEC_INPUT_FILTER_FIFO_LENGTH __BITS(5,0)
#define CEC_SPARE_REG 0x0c
#define CEC_TX_REGISTER_REG 0x10
#define CEC_TX_REGISTER_RETRY_FRAME __BIT(17)
#define CEC_TX_REGISTER_GENERATE_START_BIT __BIT(16)
#define CEC_TX_REGISTER_ADDRESS_MODE __BIT(12)
#define CEC_TX_REGISTER_EOM __BIT(8)
#define CEC_TX_REGISTER_DATA __BITS(7,0)
#define CEC_RX_REGISTER_REG 0x14
#define CEC_RX_REGISTER_ACK __BIT(9)
#define CEC_RX_REGISTER_EOM __BIT(8)
#define CEC_RX_REGISTER_DATA __BITS(7,0)
#define CEC_RX_TIMING_0_REG 0x18
#define CEC_RX_TIMING_1_REG 0x1c
#define CEC_RX_TIMING_2_REG 0x20
#define CEC_TX_TIMING_0_REG 0x24
#define CEC_TX_TIMING_1_REG 0x28
#define CEC_TX_TIMING_2_REG 0x2c
#define CEC_INT_STAT_REG 0x30
#define CEC_INT_MASK_REG 0x34
#define CEC_INT_FILTERED_RX_DATA_PIN_TRANSITION_L2H __BIT(14)
#define CEC_INT_FILTERED_RX_DATA_PIN_TRANSITION_H2L __BIT(13)
#define CEC_INT_RX_BUS_ERROR_DETECTED __BIT(12)
#define CEC_INT_RX_BUS_ANOMALY_DETECTED __BIT(11)
#define CEC_INT_RX_START_BIT_DETECTED __BIT(10)
#define CEC_INT_RX_REGISTER_OVERRUN __BIT(9)
#define CEC_INT_RX_REGISTER_FULL __BIT(8)
#define CEC_INT_TX_FRAME_TRANSMITTED __BIT(5)
#define CEC_INT_TX_BUS_ANOMALY_DETECTED __BIT(4)
#define CEC_INT_TX_ARBITRATION_FAILED __BIT(3)
#define CEC_INT_TX_FRAME_OR_BLOCK_NAKD __BIT(2)
#define CEC_INT_TX_REGISTER_UNDERRUN __BIT(1)
#define CEC_INT_TX_REGISTER_EMPTY __BIT(0)
#define CEC_HW_DEBUG_RX_REG 0x38
#define CEC_HW_DEBUG_TX_REG 0x3c
#define CEC_HW_SPARE_0_REG 0x40
#endif /* _ARM_TEGRA_CECREG_H */

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@ -1,4 +1,4 @@
/* $NetBSD: tegra_intr.h,v 1.6 2015/05/30 13:25:55 jmcneill Exp $ */
/* $NetBSD: tegra_intr.h,v 1.7 2015/08/01 21:20:11 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
@ -39,6 +39,7 @@
#define TEGRA_INTR_TMR1 TEGRA_INTR(0)
#define TEGRA_INTR_TMR2 TEGRA_INTR(1)
#define TEGRA_INTR_CEC TEGRA_INTR(3)
#define TEGRA_INTR_SDMMC1 TEGRA_INTR(14)
#define TEGRA_INTR_SDMMC2 TEGRA_INTR(15)
#define TEGRA_INTR_SDMMC3 TEGRA_INTR(19)

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@ -1,4 +1,4 @@
/* $NetBSD: tegra_io.c,v 1.12 2015/05/30 13:25:55 jmcneill Exp $ */
/* $NetBSD: tegra_io.c,v 1.13 2015/08/01 21:20:11 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
@ -29,7 +29,7 @@
#include "opt_tegra.h"
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: tegra_io.c,v 1.12 2015/05/30 13:25:55 jmcneill Exp $");
__KERNEL_RCSID(0, "$NetBSD: tegra_io.c,v 1.13 2015/08/01 21:20:11 jmcneill Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -113,6 +113,8 @@ static const struct tegra_locators tegra_apb_locators[] = {
TEGRA_SATA_OFFSET, TEGRA_SATA_SIZE, NOPORT, TEGRA_INTR_SATA },
{ "hdaudio",
TEGRA_HDA_OFFSET, TEGRA_HDA_SIZE, NOPORT, TEGRA_INTR_HDA },
{ "tegracec",
TEGRA_CEC_OFFSET, TEGRA_CEC_SIZE, NOPORT, TEGRA_INTR_CEC },
};
static const struct tegra_locators tegra_ahb_a2_locators[] = {

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@ -1,4 +1,4 @@
/* $NetBSD: tegra_reg.h,v 1.12 2015/05/30 13:25:55 jmcneill Exp $ */
/* $NetBSD: tegra_reg.h,v 1.13 2015/08/01 21:20:11 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
@ -98,6 +98,8 @@
#define TEGRA_KBC_SIZE 0x100
#define TEGRA_PMC_OFFSET 0x0000e400
#define TEGRA_PMC_SIZE 0x800
#define TEGRA_CEC_OFFSET 0x00015000
#define TEGRA_CEC_SIZE 0x1000
#define TEGRA_MC_OFFSET 0x00019000
#define TEGRA_MC_SIZE 0x1000
#define TEGRA_SATA_OFFSET 0x00020000

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@ -1,4 +1,4 @@
/* $NetBSD: tegra_var.h,v 1.23 2015/07/23 18:22:05 jmcneill Exp $ */
/* $NetBSD: tegra_var.h,v 1.24 2015/08/01 21:20:11 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
@ -101,6 +101,7 @@ int tegra_car_periph_usb_enable(u_int);
void tegra_car_periph_hda_enable(void);
void tegra_car_periph_sata_enable(void);
int tegra_car_periph_i2c_enable(u_int, u_int);
void tegra_car_periph_cec_enable(void);
void tegra_car_utmip_init(void);
void tegra_car_utmip_enable(u_int);
void tegra_car_hdmi_enable(u_int);